ArmPkg/Include/Chipset/ArmV7.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
   5
   6   SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9
  10 #ifndef ARM_V7_H_
  11 #define ARM_V7_H_
  12
  13 #include <Chipset/ArmV7Mmu.h>
  14
  15 // ARM Interrupt ID in Exception Table
  16 #define ARM_ARCH_EXCEPTION_IRQ            EXCEPT_ARM_IRQ
  17
  18 // ID_PFR1 - ARM Processor Feature Register 1 definitions
  19 #define ARM_PFR1_SEC        (0xFUL << 4)
  20 #define ARM_PFR1_TIMER      (0xFUL << 16)
  21 #define ARM_PFR1_GIC        (0xFUL << 28)
  22
  23 // Domain Access Control Register
  24 #define DOMAIN_ACCESS_CONTROL_MASK(a)     (3UL << (2 * (a)))
  25 #define DOMAIN_ACCESS_CONTROL_NONE(a)     (0UL << (2 * (a)))
  26 #define DOMAIN_ACCESS_CONTROL_CLIENT(a)   (1UL << (2 * (a)))
  27 #define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))
  28 #define DOMAIN_ACCESS_CONTROL_MANAGER(a)  (3UL << (2 * (a)))
  29
  30 // CPSR - Coprocessor Status Register definitions
  31 #define CPSR_MODE_USER       0x10
  32 #define CPSR_MODE_FIQ        0x11
  33 #define CPSR_MODE_IRQ        0x12
  34 #define CPSR_MODE_SVC        0x13
  35 #define CPSR_MODE_ABORT      0x17
  36 #define CPSR_MODE_HYP        0x1A
  37 #define CPSR_MODE_UNDEFINED  0x1B
  38 #define CPSR_MODE_SYSTEM     0x1F
  39 #define CPSR_MODE_MASK       0x1F
  40 #define CPSR_ASYNC_ABORT     (1 << 8)
  41 #define CPSR_IRQ             (1 << 7)
  42 #define CPSR_FIQ             (1 << 6)
  43
  44
  45 // CPACR - Coprocessor Access Control Register definitions
  46 #define CPACR_CP_DENIED(cp)     0x00
  47 #define CPACR_CP_PRIV(cp)       ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)
  48 #define CPACR_CP_FULL(cp)       ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)
  49 #define CPACR_ASEDIS            (1 << 31)
  50 #define CPACR_D32DIS            (1 << 30)
  51 #define CPACR_CP_FULL_ACCESS    0x0FFFFFFF
  52
  53 // NSACR - Non-Secure Access Control Register definitions
  54 #define NSACR_CP(cp)            ((1 << (cp)) & 0x3FFF)
  55 #define NSACR_NSD32DIS          (1 << 14)
  56 #define NSACR_NSASEDIS          (1 << 15)
  57 #define NSACR_PLE               (1 << 16)
  58 #define NSACR_TL                (1 << 17)
  59 #define NSACR_NS_SMP            (1 << 18)
  60 #define NSACR_RFR               (1 << 19)
  61
  62 // SCR - Secure Configuration Register definitions
  63 #define SCR_NS                  (1 << 0)
  64 #define SCR_IRQ                 (1 << 1)
  65 #define SCR_FIQ                 (1 << 2)
  66 #define SCR_EA                  (1 << 3)
  67 #define SCR_FW                  (1 << 4)
  68 #define SCR_AW                  (1 << 5)
  69
  70 // MIDR - Main ID Register definitions
  71 #define ARM_CPU_TYPE_SHIFT      4
  72 #define ARM_CPU_TYPE_MASK       0xFFF
  73 #define ARM_CPU_TYPE_AEMV8      0xD0F
  74 #define ARM_CPU_TYPE_A53        0xD03
  75 #define ARM_CPU_TYPE_A57        0xD07
  76 #define ARM_CPU_TYPE_A15        0xC0F
  77 #define ARM_CPU_TYPE_A12        0xC0D
  78 #define ARM_CPU_TYPE_A9         0xC09
  79 #define ARM_CPU_TYPE_A7         0xC07
  80 #define ARM_CPU_TYPE_A5         0xC05
  81
  82 #define ARM_CPU_REV_MASK        ((0xF << 20) | (0xF) )
  83 #define ARM_CPU_REV(rn, pn)     ((((rn) & 0xF) << 20) | ((pn) & 0xF))
  84
  85 #define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 5)-1)
  86
  87 VOID
  88 EFIAPI
  89 ArmEnableSWPInstruction (
  90   VOID
  91   );
  92
  93 UINTN
  94 EFIAPI
  95 ArmReadCbar (
  96   VOID
  97   );
  98
  99 UINTN
 100 EFIAPI
 101 ArmReadTpidrurw (
 102   VOID
 103   );
 104
 105 VOID
 106 EFIAPI
 107 ArmWriteTpidrurw (
 108   UINTN Value
 109   );
 110
 111 UINT32
 112 EFIAPI
 113 ArmReadNsacr (
 114   VOID
 115   );
 116
 117 VOID
 118 EFIAPI
 119 ArmWriteNsacr (
 120   IN  UINT32   Nsacr
 121   );
 122
 123 #endif // ARM_V7_H_