3 Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
12 #include <Uefi/UefiBaseType.h>
14 // The ARM Architecture Reference Manual for ARMv8-A defines up
15 // to 7 levels of cache, L1 through L7.
16 #define MAX_ARM_CACHE_LEVEL 7
18 /// Defines the structure of the CSSELR (Cache Size Selection) register
21 UINT32 InD
: 1; ///< Instruction not Data bit
22 UINT32 Level
: 3; ///< Cache level (zero based)
23 UINT32 TnD
: 1; ///< Allocation not Data bit
24 UINT32 Reserved
: 27; ///< Reserved, RES0
25 } Bits
; ///< Bitfield definition of the register
26 UINT32 Data
; ///< The entire 32-bit value
29 /// The cache type values for the InD field of the CSSELR register
31 /// Select the data or unified cache
32 CsselrCacheTypeDataOrUnified
= 0,
33 /// Select the instruction cache
34 CsselrCacheTypeInstruction
,
38 /// Defines the structure of the CCSIDR (Current Cache Size ID) register
41 UINT64 LineSize
: 3; ///< Line size (Log2(Num bytes in cache) - 4)
42 UINT64 Associativity
: 10; ///< Associativity - 1
43 UINT64 NumSets
: 15; ///< Number of sets in the cache -1
44 UINT64 Unknown
: 4; ///< Reserved, UNKNOWN
45 UINT64 Reserved
: 32; ///< Reserved, RES0
46 } BitsNonCcidx
; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.
48 UINT64 LineSize
: 3; ///< Line size (Log2(Num bytes in cache) - 4)
49 UINT64 Associativity
: 21; ///< Associativity - 1
50 UINT64 Reserved1
: 8; ///< Reserved, RES0
51 UINT64 NumSets
: 24; ///< Number of sets in the cache -1
52 UINT64 Reserved2
: 8; ///< Reserved, RES0
53 } BitsCcidxAA64
; ///< Bitfield definition of the register when FEAT_IDX is supported.
56 UINT64 Associativity
: 21;
58 UINT64 Unallocated
: 32;
60 UINT64 Data
; ///< The entire 64-bit value
63 /// Defines the structure of the AARCH32 CCSIDR2 register.
66 UINT32 NumSets
: 24; ///< Number of sets in the cache - 1
67 UINT32 Reserved
: 8; ///< Reserved, RES0
68 } Bits
; ///< Bitfield definition of the register
69 UINT32 Data
; ///< The entire 32-bit value
72 /** Defines the structure of the CLIDR (Cache Level ID) register.
74 * The lower 32 bits are the same for both AARCH32 and AARCH64
75 * so we can use the same structure for both.
79 UINT32 Ctype1
: 3; ///< Level 1 cache type
80 UINT32 Ctype2
: 3; ///< Level 2 cache type
81 UINT32 Ctype3
: 3; ///< Level 3 cache type
82 UINT32 Ctype4
: 3; ///< Level 4 cache type
83 UINT32 Ctype5
: 3; ///< Level 5 cache type
84 UINT32 Ctype6
: 3; ///< Level 6 cache type
85 UINT32 Ctype7
: 3; ///< Level 7 cache type
86 UINT32 LoUIS
: 3; ///< Level of Unification Inner Shareable
87 UINT32 LoC
: 3; ///< Level of Coherency
88 UINT32 LoUU
: 3; ///< Level of Unification Uniprocessor
89 UINT32 Icb
: 3; ///< Inner Cache Boundary
90 } Bits
; ///< Bitfield definition of the register
91 UINT32 Data
; ///< The entire 32-bit value
94 /// The cache types reported in the CLIDR register.
96 /// No cache is present
97 ClidrCacheTypeNone
= 0,
98 /// There is only an instruction cache
99 ClidrCacheTypeInstructionOnly
,
100 /// There is only a data cache
101 ClidrCacheTypeDataOnly
,
102 /// There are separate data and instruction caches
103 ClidrCacheTypeSeparate
,
104 /// There is a unified cache
105 ClidrCacheTypeUnified
,
109 #define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)
111 #endif /* ARM_CACHE_H_ */