ArmPkg/Include/IndustryStandard/ArmStdSmc.h

   1 /** @file
   2 *
   3 *  Copyright (c) 2012-2017, ARM Limited. All rights reserved.
   4 *
   5 *  SPDX-License-Identifier: BSD-2-Clause-Patent
   6 *
   7 **/
   8
   9 #ifndef __ARM_STD_SMC_H__
  10 #define __ARM_STD_SMC_H__
  11
  12 /*
  13  * SMC function IDs for Standard Service queries
  14  */
  15
  16 #define ARM_SMC_ID_STD_CALL_COUNT     0x8400ff00
  17 #define ARM_SMC_ID_STD_UID            0x8400ff01
  18 /*                                    0x8400ff02 is reserved */
  19 #define ARM_SMC_ID_STD_REVISION       0x8400ff03
  20
  21 /*
  22  * The 'Standard Service Call UID' is supposed to return the Standard
  23  * Service UUID. This is a 128-bit value.
  24  */
  25 #define ARM_SMC_STD_UUID0       0x108d905b
  26 #define ARM_SMC_STD_UUID1       0x47e8f863
  27 #define ARM_SMC_STD_UUID2       0xfbc02dae
  28 #define ARM_SMC_STD_UUID3       0xe2f64156
  29
  30 /*
  31  * ARM Standard Service Calls revision numbers
  32  * The current revision is:  0.1
  33  */
  34 #define ARM_SMC_STD_REVISION_MAJOR    0x0
  35 #define ARM_SMC_STD_REVISION_MINOR    0x1
  36
  37 /*
  38  * Management Mode (MM) calls cover a subset of the Standard Service Call range.
  39  * The list below is not exhaustive.
  40  */
  41 #define ARM_SMC_ID_MM_VERSION_AARCH32              0x84000040
  42 #define ARM_SMC_ID_MM_VERSION_AARCH64              0xC4000040
  43
  44 // Request service from secure standalone MM environment
  45 #define ARM_SMC_ID_MM_COMMUNICATE_AARCH32          0x84000041
  46 #define ARM_SMC_ID_MM_COMMUNICATE_AARCH64          0xC4000041
  47
  48 /* MM return error codes */
  49 #define ARM_SMC_MM_RET_SUCCESS              0
  50 #define ARM_SMC_MM_RET_NOT_SUPPORTED       -1
  51 #define ARM_SMC_MM_RET_INVALID_PARAMS      -2
  52 #define ARM_SMC_MM_RET_DENIED              -3
  53 #define ARM_SMC_MM_RET_NO_MEMORY           -4
  54
  55 /*
  56  * Power State Coordination Interface (PSCI) calls cover a subset of the
  57  * Standard Service Call range.
  58  * The list below is not exhaustive.
  59  */
  60 #define ARM_SMC_ID_PSCI_VERSION                0x84000000
  61 #define ARM_SMC_ID_PSCI_CPU_SUSPEND_AARCH64    0xc4000001
  62 #define ARM_SMC_ID_PSCI_CPU_SUSPEND_AARCH32    0x84000001
  63 #define ARM_SMC_ID_PSCI_CPU_OFF                0x84000002
  64 #define ARM_SMC_ID_PSCI_CPU_ON_AARCH64         0xc4000003
  65 #define ARM_SMC_ID_PSCI_CPU_ON_AARCH32         0x84000003
  66 #define ARM_SMC_ID_PSCI_AFFINITY_INFO_AARCH64  0xc4000004
  67 #define ARM_SMC_ID_PSCI_AFFINITY_INFO_AARCH32  0x84000004
  68 #define ARM_SMC_ID_PSCI_MIGRATE_AARCH64        0xc4000005
  69 #define ARM_SMC_ID_PSCI_MIGRATE_AARCH32        0x84000005
  70 #define ARM_SMC_ID_PSCI_SYSTEM_OFF             0x84000008
  71 #define ARM_SMC_ID_PSCI_SYSTEM_RESET           0x84000009
  72
  73 /* The current PSCI version is:  0.2 */
  74 #define ARM_SMC_PSCI_VERSION_MAJOR  0
  75 #define ARM_SMC_PSCI_VERSION_MINOR  2
  76 #define ARM_SMC_PSCI_VERSION  \
  77   ((ARM_SMC_PSCI_VERSION_MAJOR << 16) | ARM_SMC_PSCI_VERSION_MINOR)
  78
  79 /* PSCI return error codes */
  80 #define ARM_SMC_PSCI_RET_SUCCESS            0
  81 #define ARM_SMC_PSCI_RET_NOT_SUPPORTED      -1
  82 #define ARM_SMC_PSCI_RET_INVALID_PARAMS     -2
  83 #define ARM_SMC_PSCI_RET_DENIED             -3
  84 #define ARM_SMC_PSCI_RET_ALREADY_ON         -4
  85 #define ARM_SMC_PSCI_RET_ON_PENDING         -5
  86 #define ARM_SMC_PSCI_RET_INTERN_FAIL        -6
  87 #define ARM_SMC_PSCI_RET_NOT_PRESENT        -7
  88 #define ARM_SMC_PSCI_RET_DISABLED           -8
  89
  90 #define ARM_SMC_PSCI_TARGET_CPU32(Aff2, Aff1, Aff0) \
  91   ((((Aff2) & 0xFF) << 16) | (((Aff1) & 0xFF) << 8) | ((Aff0) & 0xFF))
  92
  93 #define ARM_SMC_PSCI_TARGET_CPU64(Aff3, Aff2, Aff1, Aff0) \
  94   ((((Aff3) & 0xFFULL) << 32) | (((Aff2) & 0xFF) << 16) | (((Aff1) & 0xFF) << 8) | ((Aff0) & 0xFF))
  95
  96 #define ARM_SMC_PSCI_TARGET_GET_AFF0(TargetId)  ((TargetId) & 0xFF)
  97 #define ARM_SMC_PSCI_TARGET_GET_AFF1(TargetId)  (((TargetId) >> 8) & 0xFF)
  98
  99 #define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_0    0
 100 #define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_1    1
 101 #define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_2    2
 102 #define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_3    3
 103
 104 #define ARM_SMC_ID_PSCI_AFFINITY_INFO_ON          0
 105 #define ARM_SMC_ID_PSCI_AFFINITY_INFO_OFF         1
 106 #define ARM_SMC_ID_PSCI_AFFINITY_INFO_ON_PENDING  2
 107
 108 /*
 109  * SMC function IDs for Trusted OS Service queries
 110  */
 111 #define ARM_SMC_ID_TOS_CALL_COUNT     0xbf00ff00
 112 #define ARM_SMC_ID_TOS_UID            0xbf00ff01
 113 /*                                    0xbf00ff02 is reserved */
 114 #define ARM_SMC_ID_TOS_REVISION       0xbf00ff03
 115
 116 #endif