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ArmPkg: Add PSCI 0.2 constants for system poweroff and reset
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1 /** @file
2 *
3 * Copyright (c) 2012-2014, ARM Limited. All rights reserved.
4 *
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
9 *
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12 *
13 **/
14
15 #ifndef __ARM_STD_SMC_H__
16 #define __ARM_STD_SMC_H__
17
18 /*
19 * SMC function IDs for Standard Service queries
20 */
21
22 #define ARM_SMC_ID_STD_CALL_COUNT 0x8400ff00
23 #define ARM_SMC_ID_STD_UID 0x8400ff01
24 /* 0x8400ff02 is reserved */
25 #define ARM_SMC_ID_STD_REVISION 0x8400ff03
26
27 /*
28 * The 'Standard Service Call UID' is supposed to return the Standard
29 * Service UUID. This is a 128-bit value.
30 */
31 #define ARM_SMC_STD_UUID0 0x108d905b
32 #define ARM_SMC_STD_UUID1 0x47e8f863
33 #define ARM_SMC_STD_UUID2 0xfbc02dae
34 #define ARM_SMC_STD_UUID3 0xe2f64156
35
36 /*
37 * ARM Standard Service Calls revision numbers
38 * The current revision is: 0.1
39 */
40 #define ARM_SMC_STD_REVISION_MAJOR 0x0
41 #define ARM_SMC_STD_REVISION_MINOR 0x1
42
43 /*
44 * Power State Coordination Interface (PSCI) calls cover a subset of the
45 * Standard Service Call range.
46 * The list below is not exhaustive.
47 */
48 #define ARM_SMC_ID_PSCI_VERSION 0x84000000
49 #define ARM_SMC_ID_PSCI_CPU_SUSPEND_AARCH64 0xc4000001
50 #define ARM_SMC_ID_PSCI_CPU_SUSPEND_AARCH32 0x84000001
51 #define ARM_SMC_ID_PSCI_CPU_OFF 0x84000002
52 #define ARM_SMC_ID_PSCI_CPU_ON_AARCH64 0xc4000003
53 #define ARM_SMC_ID_PSCI_CPU_ON_AARCH32 0x84000003
54 #define ARM_SMC_ID_PSCI_AFFINITY_INFO_AARCH64 0xc4000004
55 #define ARM_SMC_ID_PSCI_AFFINITY_INFO_AARCH32 0x84000004
56 #define ARM_SMC_ID_PSCI_MIGRATE_AARCH64 0xc4000005
57 #define ARM_SMC_ID_PSCI_MIGRATE_AARCH32 0x84000005
58 #define ARM_SMC_ID_PSCI_SYSTEM_OFF 0x84000008
59 #define ARM_SMC_ID_PSCI_SYSTEM_RESET 0x84000009
60
61 /* The current PSCI version is: 0.2 */
62 #define ARM_SMC_PSCI_VERSION_MAJOR 0
63 #define ARM_SMC_PSCI_VERSION_MINOR 2
64 #define ARM_SMC_PSCI_VERSION \
65 ((ARM_SMC_PSCI_VERSION_MAJOR << 16) | ARM_SMC_PSCI_VERSION_MINOR)
66
67 /* PSCI return error codes */
68 #define ARM_SMC_PSCI_RET_SUCCESS 0
69 #define ARM_SMC_PSCI_RET_NOT_SUPPORTED -1
70 #define ARM_SMC_PSCI_RET_INVALID_PARAMS -2
71 #define ARM_SMC_PSCI_RET_DENIED -3
72 #define ARM_SMC_PSCI_RET_ALREADY_ON -4
73 #define ARM_SMC_PSCI_RET_ON_PENDING -5
74 #define ARM_SMC_PSCI_RET_INTERN_FAIL -6
75 #define ARM_SMC_PSCI_RET_NOT_PRESENT -7
76 #define ARM_SMC_PSCI_RET_DISABLED -8
77
78 #define ARM_SMC_PSCI_TARGET_CPU32(Aff2, Aff1, Aff0) \
79 ((((Aff2) & 0xFF) << 16) | (((Aff1) & 0xFF) << 8) | ((Aff0) & 0xFF))
80
81 #define ARM_SMC_PSCI_TARGET_CPU64(Aff3, Aff2, Aff1, Aff0) \
82 ((((Aff3) & 0xFFULL) << 32) | (((Aff2) & 0xFF) << 16) | (((Aff1) & 0xFF) << 8) | ((Aff0) & 0xFF))
83
84 #define ARM_SMC_PSCI_TARGET_GET_AFF0(TargetId) ((TargetId) & 0xFF)
85 #define ARM_SMC_PSCI_TARGET_GET_AFF1(TargetId) (((TargetId) >> 8) & 0xFF)
86
87 #define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_0 0
88 #define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_1 1
89 #define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_2 2
90 #define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_3 3
91
92 #define ARM_SMC_ID_PSCI_AFFINITY_INFO_ON 0
93 #define ARM_SMC_ID_PSCI_AFFINITY_INFO_OFF 1
94 #define ARM_SMC_ID_PSCI_AFFINITY_INFO_ON_PENDING 2
95
96 #endif