3 * Copyright (c) 2011-2015, ARM Limited. All rights reserved.
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
22 ARM_GIC_ARCH_REVISION_2
,
23 ARM_GIC_ARCH_REVISION_3
24 } ARM_GIC_ARCH_REVISION
;
29 #define ARM_GIC_ICDDCR 0x000 // Distributor Control Register
30 #define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register
31 #define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register
33 // Each reg base below repeats for Number of interrupts / 4 (see GIC spec)
34 #define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers
35 #define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers
36 #define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers
37 #define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers
38 #define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers
39 #define ARM_GIC_ICDABR 0x300 // Active Bit Registers
41 // Each reg base below repeats for Number of interrupts / 4
42 #define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers
44 // Each reg base below repeats for Number of interrupts
45 #define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers
46 #define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers
48 #define ARM_GIC_ICDPPISR 0xD00 // PPI Status register
51 #define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register
53 // GICv3 specific registers
54 #define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers
60 #define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB
61 #define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB
63 // GIC Redistributor Control frame
64 #define ARM_GICR_TYPER 0x0008 // Redistributor Type Register
66 // GIC SGI & PPI Redistributor frame
67 #define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers
68 #define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Registers
73 #define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register
74 #define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register
75 #define ARM_GIC_ICCBPR 0x08 // Binary Point Register
76 #define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register
77 #define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register
78 #define ARM_GIC_ICCRPR 0x14 // Running Priority Register
79 #define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register
80 #define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register
81 #define ARM_GIC_ICCIIDR 0xFC // Identification Register
83 #define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0
84 #define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1
85 #define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2
87 // Bit-masks to configure the CPU Interface Control register
88 #define ARM_GIC_ICCICR_ENABLE_SECURE 0x01
89 #define ARM_GIC_ICCICR_ENABLE_NS 0x02
90 #define ARM_GIC_ICCICR_ACK_CTL 0x04
91 #define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08
92 #define ARM_GIC_ICCICR_USE_SBPR 0x10
94 // Bit Mask for GICC_IIDR
95 #define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr) (((IccIidr) >> 20) & 0xFFF)
96 #define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)
97 #define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF)
98 #define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF)
101 #define ARM_GIC_ICCIAR_ACKINTID 0x3FF
103 ARM_GIC_ARCH_REVISION
105 ArmGicGetSupportedArchRevision (
111 ArmGicGetInterfaceIdentification (
112 IN INTN GicInterruptInterfaceBase
116 // GIC Secure interfaces
120 ArmGicSetupNonSecure (
122 IN INTN GicDistributorBase
,
123 IN INTN GicInterruptInterfaceBase
128 ArmGicSetSecureInterrupts (
129 IN UINTN GicDistributorBase
,
130 IN UINTN
* GicSecureInterruptMask
,
131 IN UINTN GicSecureInterruptMaskSize
136 ArmGicEnableInterruptInterface (
137 IN INTN GicInterruptInterfaceBase
142 ArmGicDisableInterruptInterface (
143 IN INTN GicInterruptInterfaceBase
148 ArmGicEnableDistributor (
149 IN INTN GicDistributorBase
154 ArmGicDisableDistributor (
155 IN INTN GicDistributorBase
160 ArmGicGetMaxNumInterrupts (
161 IN INTN GicDistributorBase
167 IN INTN GicDistributorBase
,
168 IN INTN TargetListFilter
,
169 IN INTN CPUTargetList
,
174 * Acknowledge and return the value of the Interrupt Acknowledge Register
176 * InterruptId is returned separately from the register value because in
177 * the GICv2 the register value contains the CpuId and InterruptId while
178 * in the GICv3 the register value is only the InterruptId.
180 * @param GicInterruptInterfaceBase Base Address of the GIC CPU Interface
181 * @param InterruptId InterruptId read from the Interrupt Acknowledge Register
183 * @retval value returned by the Interrupt Acknowledge Register
188 ArmGicAcknowledgeInterrupt (
189 IN UINTN GicInterruptInterfaceBase
,
190 OUT UINTN
*InterruptId
195 ArmGicEndOfInterrupt (
196 IN UINTN GicInterruptInterfaceBase
,
202 ArmGicSetPriorityMask (
203 IN INTN GicInterruptInterfaceBase
,
209 ArmGicEnableInterrupt (
210 IN UINTN GicDistributorBase
,
211 IN UINTN GicRedistributorBase
,
217 ArmGicDisableInterrupt (
218 IN UINTN GicDistributorBase
,
219 IN UINTN GicRedistributorBase
,
225 ArmGicIsInterruptEnabled (
226 IN UINTN GicDistributorBase
,
227 IN UINTN GicRedistributorBase
,