ArmPkg/Include/Library/ArmGicLib.h

   1 /** @file
   2 *
   3 *  Copyright (c) 2011-2017, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #ifndef __ARMGIC_H
  16 #define __ARMGIC_H
  17
  18 #include <Library/ArmGicArchLib.h>
  19
  20 // GIC Distributor
  21 #define ARM_GIC_ICDDCR          0x000 // Distributor Control Register
  22 #define ARM_GIC_ICDICTR         0x004 // Interrupt Controller Type Register
  23 #define ARM_GIC_ICDIIDR         0x008 // Implementer Identification Register
  24
  25 // Each reg base below repeats for Number of interrupts / 4 (see GIC spec)
  26 #define ARM_GIC_ICDISR          0x080 // Interrupt Security Registers
  27 #define ARM_GIC_ICDISER         0x100 // Interrupt Set-Enable Registers
  28 #define ARM_GIC_ICDICER         0x180 // Interrupt Clear-Enable Registers
  29 #define ARM_GIC_ICDSPR          0x200 // Interrupt Set-Pending Registers
  30 #define ARM_GIC_ICDICPR         0x280 // Interrupt Clear-Pending Registers
  31 #define ARM_GIC_ICDABR          0x300 // Active Bit Registers
  32
  33 // Each reg base below repeats for Number of interrupts / 4
  34 #define ARM_GIC_ICDIPR          0x400 // Interrupt Priority Registers
  35
  36 // Each reg base below repeats for Number of interrupts
  37 #define ARM_GIC_ICDIPTR         0x800 // Interrupt Processor Target Registers
  38 #define ARM_GIC_ICDICFR         0xC00 // Interrupt Configuration Registers
  39
  40 #define ARM_GIC_ICDPPISR        0xD00 // PPI Status register
  41
  42 // just one of these
  43 #define ARM_GIC_ICDSGIR         0xF00 // Software Generated Interrupt Register
  44
  45 // GICv3 specific registers
  46 #define ARM_GICD_IROUTER        0x6100 // Interrupt Routing Registers
  47
  48 // GICD_CTLR bits
  49 #define ARM_GIC_ICDDCR_ARE      (1 << 4) // Affinity Routing Enable (ARE)
  50 #define ARM_GIC_ICDDCR_DS       (1 << 6) // Disable Security (DS)
  51
  52 // GICD_ICDICFR bits
  53 #define ARM_GIC_ICDICFR_WIDTH            32   // ICDICFR is a 32 bit register
  54 #define ARM_GIC_ICDICFR_BYTES            (ARM_GIC_ICDICFR_WIDTH / 8)
  55 #define ARM_GIC_ICDICFR_F_WIDTH          2    // Each F field is 2 bits
  56 #define ARM_GIC_ICDICFR_F_STRIDE         16   // (32/2) F fields per register
  57 #define ARM_GIC_ICDICFR_F_CONFIG1_BIT    1    // Bit number within F field
  58 #define ARM_GIC_ICDICFR_LEVEL_TRIGGERED  0x0  // Level triggered interrupt
  59 #define ARM_GIC_ICDICFR_EDGE_TRIGGERED   0x1  // Edge triggered interrupt
  60
  61
  62 // GIC Redistributor
  63 #define ARM_GICR_CTLR_FRAME_SIZE    SIZE_64KB
  64 #define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB
  65
  66 // GIC Redistributor Control frame
  67 #define ARM_GICR_TYPER          0x0008  // Redistributor Type Register
  68
  69 // GIC SGI & PPI Redistributor frame
  70 #define ARM_GICR_ISENABLER      0x0100  // Interrupt Set-Enable Registers
  71 #define ARM_GICR_ICENABLER      0x0180  // Interrupt Clear-Enable Registers
  72
  73 // GIC Cpu interface
  74 #define ARM_GIC_ICCICR          0x00  // CPU Interface Control Register
  75 #define ARM_GIC_ICCPMR          0x04  // Interrupt Priority Mask Register
  76 #define ARM_GIC_ICCBPR          0x08  // Binary Point Register
  77 #define ARM_GIC_ICCIAR          0x0C  // Interrupt Acknowledge Register
  78 #define ARM_GIC_ICCEIOR         0x10  // End Of Interrupt Register
  79 #define ARM_GIC_ICCRPR          0x14  // Running Priority Register
  80 #define ARM_GIC_ICCPIR          0x18  // Highest Pending Interrupt Register
  81 #define ARM_GIC_ICCABPR         0x1C  // Aliased Binary Point Register
  82 #define ARM_GIC_ICCIIDR         0xFC  // Identification Register
  83
  84 #define ARM_GIC_ICDSGIR_FILTER_TARGETLIST       0x0
  85 #define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE     0x1
  86 #define ARM_GIC_ICDSGIR_FILTER_ITSELF           0x2
  87
  88 // Bit-masks to configure the CPU Interface Control register
  89 #define ARM_GIC_ICCICR_ENABLE_SECURE            0x01
  90 #define ARM_GIC_ICCICR_ENABLE_NS                0x02
  91 #define ARM_GIC_ICCICR_ACK_CTL                  0x04
  92 #define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ     0x08
  93 #define ARM_GIC_ICCICR_USE_SBPR                 0x10
  94
  95 // Bit Mask for GICC_IIDR
  96 #define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr)   (((IccIidr) >> 20) & 0xFFF)
  97 #define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)
  98 #define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr)     (((IccIidr) >> 12) & 0xF)
  99 #define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr)  ((IccIidr) & 0xFFF)
 100
 101 // Bit Mask for
 102 #define ARM_GIC_ICCIAR_ACKINTID                 0x3FF
 103
 104 UINTN
 105 EFIAPI
 106 ArmGicGetInterfaceIdentification (
 107   IN  INTN          GicInterruptInterfaceBase
 108   );
 109
 110 // GIC Secure interfaces
 111 VOID
 112 EFIAPI
 113 ArmGicSetupNonSecure (
 114   IN  UINTN         MpId,
 115   IN  INTN          GicDistributorBase,
 116   IN  INTN          GicInterruptInterfaceBase
 117   );
 118
 119 VOID
 120 EFIAPI
 121 ArmGicSetSecureInterrupts (
 122   IN  UINTN         GicDistributorBase,
 123   IN  UINTN*        GicSecureInterruptMask,
 124   IN  UINTN         GicSecureInterruptMaskSize
 125   );
 126
 127 VOID
 128 EFIAPI
 129 ArmGicEnableInterruptInterface (
 130   IN  INTN          GicInterruptInterfaceBase
 131   );
 132
 133 VOID
 134 EFIAPI
 135 ArmGicDisableInterruptInterface (
 136   IN  INTN          GicInterruptInterfaceBase
 137   );
 138
 139 VOID
 140 EFIAPI
 141 ArmGicEnableDistributor (
 142   IN  INTN          GicDistributorBase
 143   );
 144
 145 VOID
 146 EFIAPI
 147 ArmGicDisableDistributor (
 148   IN  INTN          GicDistributorBase
 149   );
 150
 151 UINTN
 152 EFIAPI
 153 ArmGicGetMaxNumInterrupts (
 154   IN  INTN          GicDistributorBase
 155   );
 156
 157 VOID
 158 EFIAPI
 159 ArmGicSendSgiTo (
 160   IN  INTN          GicDistributorBase,
 161   IN  INTN          TargetListFilter,
 162   IN  INTN          CPUTargetList,
 163   IN  INTN          SgiId
 164   );
 165
 166 /*
 167  * Acknowledge and return the value of the Interrupt Acknowledge Register
 168  *
 169  * InterruptId is returned separately from the register value because in
 170  * the GICv2 the register value contains the CpuId and InterruptId while
 171  * in the GICv3 the register value is only the InterruptId.
 172  *
 173  * @param GicInterruptInterfaceBase   Base Address of the GIC CPU Interface
 174  * @param InterruptId                 InterruptId read from the Interrupt
 175  *                                    Acknowledge Register
 176  *
 177  * @retval value returned by the Interrupt Acknowledge Register
 178  *
 179  */
 180 UINTN
 181 EFIAPI
 182 ArmGicAcknowledgeInterrupt (
 183   IN  UINTN          GicInterruptInterfaceBase,
 184   OUT UINTN          *InterruptId
 185   );
 186
 187 VOID
 188 EFIAPI
 189 ArmGicEndOfInterrupt (
 190   IN  UINTN                 GicInterruptInterfaceBase,
 191   IN UINTN                  Source
 192   );
 193
 194 UINTN
 195 EFIAPI
 196 ArmGicSetPriorityMask (
 197   IN  INTN          GicInterruptInterfaceBase,
 198   IN  INTN          PriorityMask
 199   );
 200
 201 VOID
 202 EFIAPI
 203 ArmGicEnableInterrupt (
 204   IN UINTN                  GicDistributorBase,
 205   IN UINTN                  GicRedistributorBase,
 206   IN UINTN                  Source
 207   );
 208
 209 VOID
 210 EFIAPI
 211 ArmGicDisableInterrupt (
 212   IN UINTN                  GicDistributorBase,
 213   IN UINTN                  GicRedistributorBase,
 214   IN UINTN                  Source
 215   );
 216
 217 BOOLEAN
 218 EFIAPI
 219 ArmGicIsInterruptEnabled (
 220   IN UINTN                  GicDistributorBase,
 221   IN UINTN                  GicRedistributorBase,
 222   IN UINTN                  Source
 223   );
 224
 225 // GIC revision 2 specific declarations
 226
 227 // Interrupts from 1020 to 1023 are considered as special interrupts
 228 // (eg: spurious interrupts)
 229 #define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) \
 230           (((Interrupt) >= 1020) && ((Interrupt) <= 1023))
 231
 232 VOID
 233 EFIAPI
 234 ArmGicV2SetupNonSecure (
 235   IN  UINTN         MpId,
 236   IN  INTN          GicDistributorBase,
 237   IN  INTN          GicInterruptInterfaceBase
 238   );
 239
 240 VOID
 241 EFIAPI
 242 ArmGicV2EnableInterruptInterface (
 243   IN  INTN          GicInterruptInterfaceBase
 244   );
 245
 246 VOID
 247 EFIAPI
 248 ArmGicV2DisableInterruptInterface (
 249   IN  INTN          GicInterruptInterfaceBase
 250   );
 251
 252 UINTN
 253 EFIAPI
 254 ArmGicV2AcknowledgeInterrupt (
 255   IN  UINTN          GicInterruptInterfaceBase
 256   );
 257
 258 VOID
 259 EFIAPI
 260 ArmGicV2EndOfInterrupt (
 261   IN UINTN                  GicInterruptInterfaceBase,
 262   IN UINTN                  Source
 263   );
 264
 265 // GIC revision 3 specific declarations
 266
 267 #define ICC_SRE_EL2_SRE         (1 << 0)
 268
 269 #define ARM_GICD_IROUTER_IRM BIT31
 270
 271 UINT32
 272 EFIAPI
 273 ArmGicV3GetControlSystemRegisterEnable (
 274   VOID
 275   );
 276
 277 VOID
 278 EFIAPI
 279 ArmGicV3SetControlSystemRegisterEnable (
 280   IN UINT32         ControlSystemRegisterEnable
 281   );
 282
 283 VOID
 284 EFIAPI
 285 ArmGicV3EnableInterruptInterface (
 286   VOID
 287   );
 288
 289 VOID
 290 EFIAPI
 291 ArmGicV3DisableInterruptInterface (
 292   VOID
 293   );
 294
 295 UINTN
 296 EFIAPI
 297 ArmGicV3AcknowledgeInterrupt (
 298   VOID
 299   );
 300
 301 VOID
 302 EFIAPI
 303 ArmGicV3EndOfInterrupt (
 304   IN UINTN                  Source
 305   );
 306
 307 VOID
 308 ArmGicV3SetBinaryPointer (
 309   IN UINTN                  BinaryPoint
 310   );
 311
 312 VOID
 313 ArmGicV3SetPriorityMask (
 314   IN UINTN                  Priority
 315   );
 316
 317 #endif