3 * Copyright (c) 2011-2018, ARM Limited. All rights reserved.
5 * SPDX-License-Identifier: BSD-2-Clause-Patent
12 #include <Library/ArmGicArchLib.h>
15 #define ARM_GIC_ICDDCR 0x000 // Distributor Control Register
16 #define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register
17 #define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register
19 // Each reg base below repeats for Number of interrupts / 4 (see GIC spec)
20 #define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers
21 #define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers
22 #define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers
23 #define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers
24 #define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers
25 #define ARM_GIC_ICDABR 0x300 // Active Bit Registers
27 // Each reg base below repeats for Number of interrupts / 4
28 #define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers
30 // Each reg base below repeats for Number of interrupts
31 #define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers
32 #define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers
34 #define ARM_GIC_ICDPPISR 0xD00 // PPI Status register
37 #define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register
39 // GICv3 specific registers
40 #define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers
43 #define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE)
44 #define ARM_GIC_ICDDCR_DS (1 << 6) // Disable Security (DS)
47 #define ARM_GIC_ICDICFR_WIDTH 32 // ICDICFR is a 32 bit register
48 #define ARM_GIC_ICDICFR_BYTES (ARM_GIC_ICDICFR_WIDTH / 8)
49 #define ARM_GIC_ICDICFR_F_WIDTH 2 // Each F field is 2 bits
50 #define ARM_GIC_ICDICFR_F_STRIDE 16 // (32/2) F fields per register
51 #define ARM_GIC_ICDICFR_F_CONFIG1_BIT 1 // Bit number within F field
52 #define ARM_GIC_ICDICFR_LEVEL_TRIGGERED 0x0 // Level triggered interrupt
53 #define ARM_GIC_ICDICFR_EDGE_TRIGGERED 0x1 // Edge triggered interrupt
57 #define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB
58 #define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB
59 #define ARM_GICR_SGI_VLPI_FRAME_SIZE SIZE_64KB
60 #define ARM_GICR_SGI_RESERVED_FRAME_SIZE SIZE_64KB
62 // GIC Redistributor Control frame
63 #define ARM_GICR_TYPER 0x0008 // Redistributor Type Register
65 // GIC Redistributor TYPER bit assignments
66 #define ARM_GICR_TYPER_PLPIS (1 << 0) // Physical LPIs
67 #define ARM_GICR_TYPER_VLPIS (1 << 1) // Virtual LPIs
68 #define ARM_GICR_TYPER_DIRECTLPI (1 << 3) // Direct LPIs
69 #define ARM_GICR_TYPER_LAST (1 << 4) // Last Redistributor in series
70 #define ARM_GICR_TYPER_DPGS (1 << 5) // Disable Processor Group
72 #define ARM_GICR_TYPER_PROCNO (0xFFFF << 8) // Processor Number
73 #define ARM_GICR_TYPER_COMMONLPIAFF (0x3 << 24) // Common LPI Affinity
74 #define ARM_GICR_TYPER_AFFINITY (0xFFFFFFFFULL << 32) // Redistributor Affinity
76 #define ARM_GICR_TYPER_GET_AFFINITY(TypeReg) (((TypeReg) & \
77 ARM_GICR_TYPER_AFFINITY) >> 32)
79 // GIC SGI & PPI Redistributor frame
80 #define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers
81 #define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Registers
84 #define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register
85 #define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register
86 #define ARM_GIC_ICCBPR 0x08 // Binary Point Register
87 #define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register
88 #define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register
89 #define ARM_GIC_ICCRPR 0x14 // Running Priority Register
90 #define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register
91 #define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register
92 #define ARM_GIC_ICCIIDR 0xFC // Identification Register
94 #define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0
95 #define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1
96 #define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2
98 // Bit-masks to configure the CPU Interface Control register
99 #define ARM_GIC_ICCICR_ENABLE_SECURE 0x01
100 #define ARM_GIC_ICCICR_ENABLE_NS 0x02
101 #define ARM_GIC_ICCICR_ACK_CTL 0x04
102 #define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08
103 #define ARM_GIC_ICCICR_USE_SBPR 0x10
105 // Bit Mask for GICC_IIDR
106 #define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr) (((IccIidr) >> 20) & 0xFFF)
107 #define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)
108 #define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF)
109 #define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF)
112 #define ARM_GIC_ICCIAR_ACKINTID 0x3FF
116 ArmGicGetInterfaceIdentification (
117 IN INTN GicInterruptInterfaceBase
120 // GIC Secure interfaces
123 ArmGicSetupNonSecure (
125 IN INTN GicDistributorBase
,
126 IN INTN GicInterruptInterfaceBase
131 ArmGicSetSecureInterrupts (
132 IN UINTN GicDistributorBase
,
133 IN UINTN
* GicSecureInterruptMask
,
134 IN UINTN GicSecureInterruptMaskSize
139 ArmGicEnableInterruptInterface (
140 IN INTN GicInterruptInterfaceBase
145 ArmGicDisableInterruptInterface (
146 IN INTN GicInterruptInterfaceBase
151 ArmGicEnableDistributor (
152 IN INTN GicDistributorBase
157 ArmGicDisableDistributor (
158 IN INTN GicDistributorBase
163 ArmGicGetMaxNumInterrupts (
164 IN INTN GicDistributorBase
170 IN INTN GicDistributorBase
,
171 IN INTN TargetListFilter
,
172 IN INTN CPUTargetList
,
177 * Acknowledge and return the value of the Interrupt Acknowledge Register
179 * InterruptId is returned separately from the register value because in
180 * the GICv2 the register value contains the CpuId and InterruptId while
181 * in the GICv3 the register value is only the InterruptId.
183 * @param GicInterruptInterfaceBase Base Address of the GIC CPU Interface
184 * @param InterruptId InterruptId read from the Interrupt
185 * Acknowledge Register
187 * @retval value returned by the Interrupt Acknowledge Register
192 ArmGicAcknowledgeInterrupt (
193 IN UINTN GicInterruptInterfaceBase
,
194 OUT UINTN
*InterruptId
199 ArmGicEndOfInterrupt (
200 IN UINTN GicInterruptInterfaceBase
,
206 ArmGicSetPriorityMask (
207 IN INTN GicInterruptInterfaceBase
,
213 ArmGicEnableInterrupt (
214 IN UINTN GicDistributorBase
,
215 IN UINTN GicRedistributorBase
,
221 ArmGicDisableInterrupt (
222 IN UINTN GicDistributorBase
,
223 IN UINTN GicRedistributorBase
,
229 ArmGicIsInterruptEnabled (
230 IN UINTN GicDistributorBase
,
231 IN UINTN GicRedistributorBase
,
235 // GIC revision 2 specific declarations
237 // Interrupts from 1020 to 1023 are considered as special interrupts
238 // (eg: spurious interrupts)
239 #define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) \
240 (((Interrupt) >= 1020) && ((Interrupt) <= 1023))
244 ArmGicV2SetupNonSecure (
246 IN INTN GicDistributorBase
,
247 IN INTN GicInterruptInterfaceBase
252 ArmGicV2EnableInterruptInterface (
253 IN INTN GicInterruptInterfaceBase
258 ArmGicV2DisableInterruptInterface (
259 IN INTN GicInterruptInterfaceBase
264 ArmGicV2AcknowledgeInterrupt (
265 IN UINTN GicInterruptInterfaceBase
270 ArmGicV2EndOfInterrupt (
271 IN UINTN GicInterruptInterfaceBase
,
275 // GIC revision 3 specific declarations
277 #define ICC_SRE_EL2_SRE (1 << 0)
279 #define ARM_GICD_IROUTER_IRM BIT31
283 ArmGicV3GetControlSystemRegisterEnable (
289 ArmGicV3SetControlSystemRegisterEnable (
290 IN UINT32 ControlSystemRegisterEnable
295 ArmGicV3EnableInterruptInterface (
301 ArmGicV3DisableInterruptInterface (
307 ArmGicV3AcknowledgeInterrupt (
313 ArmGicV3EndOfInterrupt (
318 ArmGicV3SetBinaryPointer (
323 ArmGicV3SetPriorityMask (