ArmPkg/Include/Library/ArmGicLib.h

   1 /** @file
   2 *
   3 *  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #ifndef __ARMGIC_H
  16 #define __ARMGIC_H
  17
  18 //
  19 // GIC definitions
  20 //
  21 typedef enum {
  22   ARM_GIC_ARCH_REVISION_2,
  23   ARM_GIC_ARCH_REVISION_3
  24 } ARM_GIC_ARCH_REVISION;
  25
  26 //
  27 // GIC Distributor
  28 //
  29 #define ARM_GIC_ICDDCR          0x000 // Distributor Control Register
  30 #define ARM_GIC_ICDICTR         0x004 // Interrupt Controller Type Register
  31 #define ARM_GIC_ICDIIDR         0x008 // Implementer Identification Register
  32
  33 // Each reg base below repeats for Number of interrupts / 4 (see GIC spec)
  34 #define ARM_GIC_ICDISR          0x080 // Interrupt Security Registers
  35 #define ARM_GIC_ICDISER         0x100 // Interrupt Set-Enable Registers
  36 #define ARM_GIC_ICDICER         0x180 // Interrupt Clear-Enable Registers
  37 #define ARM_GIC_ICDSPR          0x200 // Interrupt Set-Pending Registers
  38 #define ARM_GIC_ICDICPR         0x280 // Interrupt Clear-Pending Registers
  39 #define ARM_GIC_ICDABR          0x300 // Active Bit Registers
  40
  41 // Each reg base below repeats for Number of interrupts / 4
  42 #define ARM_GIC_ICDIPR          0x400 // Interrupt Priority Registers
  43
  44 // Each reg base below repeats for Number of interrupts
  45 #define ARM_GIC_ICDIPTR         0x800 // Interrupt Processor Target Registers
  46 #define ARM_GIC_ICDICFR         0xC00 // Interrupt Configuration Registers
  47
  48 #define ARM_GIC_ICDPPISR        0xD00 // PPI Status register
  49
  50 // just one of these
  51 #define ARM_GIC_ICDSGIR         0xF00 // Software Generated Interrupt Register
  52
  53 // GICv3 specific registers
  54 #define ARM_GICD_IROUTER        0x6100 // Interrupt Routing Registers
  55
  56 // the Affinity Routing Enable (ARE) bit in GICD_CTLR
  57 #define ARM_GIC_ICDDCR_ARE      (1 << 4)
  58
  59 //
  60 // GIC Redistributor
  61 //
  62
  63 #define ARM_GICR_CTLR_FRAME_SIZE    SIZE_64KB
  64 #define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB
  65
  66 // GIC Redistributor Control frame
  67 #define ARM_GICR_TYPER          0x0008  // Redistributor Type Register
  68
  69 // GIC SGI & PPI Redistributor frame
  70 #define ARM_GICR_ISENABLER      0x0100  // Interrupt Set-Enable Registers
  71 #define ARM_GICR_ICENABLER      0x0180  // Interrupt Clear-Enable Registers
  72
  73 //
  74 // GIC Cpu interface
  75 //
  76 #define ARM_GIC_ICCICR          0x00  // CPU Interface Control Register
  77 #define ARM_GIC_ICCPMR          0x04  // Interrupt Priority Mask Register
  78 #define ARM_GIC_ICCBPR          0x08  // Binary Point Register
  79 #define ARM_GIC_ICCIAR          0x0C  // Interrupt Acknowledge Register
  80 #define ARM_GIC_ICCEIOR         0x10  // End Of Interrupt Register
  81 #define ARM_GIC_ICCRPR          0x14  // Running Priority Register
  82 #define ARM_GIC_ICCPIR          0x18  // Highest Pending Interrupt Register
  83 #define ARM_GIC_ICCABPR         0x1C  // Aliased Binary Point Register
  84 #define ARM_GIC_ICCIIDR         0xFC  // Identification Register
  85
  86 #define ARM_GIC_ICDSGIR_FILTER_TARGETLIST       0x0
  87 #define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE     0x1
  88 #define ARM_GIC_ICDSGIR_FILTER_ITSELF           0x2
  89
  90 // Bit-masks to configure the CPU Interface Control register
  91 #define ARM_GIC_ICCICR_ENABLE_SECURE            0x01
  92 #define ARM_GIC_ICCICR_ENABLE_NS                0x02
  93 #define ARM_GIC_ICCICR_ACK_CTL                  0x04
  94 #define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ     0x08
  95 #define ARM_GIC_ICCICR_USE_SBPR                 0x10
  96
  97 // Bit Mask for GICC_IIDR
  98 #define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr)   (((IccIidr) >> 20) & 0xFFF)
  99 #define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)
 100 #define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr)     (((IccIidr) >> 12) & 0xF)
 101 #define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr)  ((IccIidr) & 0xFFF)
 102
 103 // Bit Mask for
 104 #define ARM_GIC_ICCIAR_ACKINTID                 0x3FF
 105
 106 ARM_GIC_ARCH_REVISION
 107 EFIAPI
 108 ArmGicGetSupportedArchRevision (
 109   VOID
 110   );
 111
 112 UINTN
 113 EFIAPI
 114 ArmGicGetInterfaceIdentification (
 115   IN  INTN          GicInterruptInterfaceBase
 116   );
 117
 118 //
 119 // GIC Secure interfaces
 120 //
 121 VOID
 122 EFIAPI
 123 ArmGicSetupNonSecure (
 124   IN  UINTN         MpId,
 125   IN  INTN          GicDistributorBase,
 126   IN  INTN          GicInterruptInterfaceBase
 127   );
 128
 129 VOID
 130 EFIAPI
 131 ArmGicSetSecureInterrupts (
 132   IN  UINTN         GicDistributorBase,
 133   IN  UINTN*        GicSecureInterruptMask,
 134   IN  UINTN         GicSecureInterruptMaskSize
 135   );
 136
 137 VOID
 138 EFIAPI
 139 ArmGicEnableInterruptInterface (
 140   IN  INTN          GicInterruptInterfaceBase
 141   );
 142
 143 VOID
 144 EFIAPI
 145 ArmGicDisableInterruptInterface (
 146   IN  INTN          GicInterruptInterfaceBase
 147   );
 148
 149 VOID
 150 EFIAPI
 151 ArmGicEnableDistributor (
 152   IN  INTN          GicDistributorBase
 153   );
 154
 155 VOID
 156 EFIAPI
 157 ArmGicDisableDistributor (
 158   IN  INTN          GicDistributorBase
 159   );
 160
 161 UINTN
 162 EFIAPI
 163 ArmGicGetMaxNumInterrupts (
 164   IN  INTN          GicDistributorBase
 165   );
 166
 167 VOID
 168 EFIAPI
 169 ArmGicSendSgiTo (
 170   IN  INTN          GicDistributorBase,
 171   IN  INTN          TargetListFilter,
 172   IN  INTN          CPUTargetList,
 173   IN  INTN          SgiId
 174   );
 175
 176 /*
 177  * Acknowledge and return the value of the Interrupt Acknowledge Register
 178  *
 179  * InterruptId is returned separately from the register value because in
 180  * the GICv2 the register value contains the CpuId and InterruptId while
 181  * in the GICv3 the register value is only the InterruptId.
 182  *
 183  * @param GicInterruptInterfaceBase   Base Address of the GIC CPU Interface
 184  * @param InterruptId                 InterruptId read from the Interrupt Acknowledge Register
 185  *
 186  * @retval value returned by the Interrupt Acknowledge Register
 187  *
 188  */
 189 UINTN
 190 EFIAPI
 191 ArmGicAcknowledgeInterrupt (
 192   IN  UINTN          GicInterruptInterfaceBase,
 193   OUT UINTN          *InterruptId
 194   );
 195
 196 VOID
 197 EFIAPI
 198 ArmGicEndOfInterrupt (
 199   IN  UINTN                 GicInterruptInterfaceBase,
 200   IN UINTN                  Source
 201   );
 202
 203 UINTN
 204 EFIAPI
 205 ArmGicSetPriorityMask (
 206   IN  INTN          GicInterruptInterfaceBase,
 207   IN  INTN          PriorityMask
 208   );
 209
 210 VOID
 211 EFIAPI
 212 ArmGicEnableInterrupt (
 213   IN UINTN                  GicDistributorBase,
 214   IN UINTN                  GicRedistributorBase,
 215   IN UINTN                  Source
 216   );
 217
 218 VOID
 219 EFIAPI
 220 ArmGicDisableInterrupt (
 221   IN UINTN                  GicDistributorBase,
 222   IN UINTN                  GicRedistributorBase,
 223   IN UINTN                  Source
 224   );
 225
 226 BOOLEAN
 227 EFIAPI
 228 ArmGicIsInterruptEnabled (
 229   IN UINTN                  GicDistributorBase,
 230   IN UINTN                  GicRedistributorBase,
 231   IN UINTN                  Source
 232   );
 233
 234 //
 235 // GIC revision 2 specific declarations
 236 //
 237
 238 // Interrupts from 1020 to 1023 are considered as special interrupts (eg: spurious interrupts)
 239 #define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) (((Interrupt) >= 1020) && ((Interrupt) <= 1023))
 240
 241 VOID
 242 EFIAPI
 243 ArmGicV2SetupNonSecure (
 244   IN  UINTN         MpId,
 245   IN  INTN          GicDistributorBase,
 246   IN  INTN          GicInterruptInterfaceBase
 247   );
 248
 249 VOID
 250 EFIAPI
 251 ArmGicV2EnableInterruptInterface (
 252   IN  INTN          GicInterruptInterfaceBase
 253   );
 254
 255 VOID
 256 EFIAPI
 257 ArmGicV2DisableInterruptInterface (
 258   IN  INTN          GicInterruptInterfaceBase
 259   );
 260
 261 UINTN
 262 EFIAPI
 263 ArmGicV2AcknowledgeInterrupt (
 264   IN  UINTN          GicInterruptInterfaceBase
 265   );
 266
 267 VOID
 268 EFIAPI
 269 ArmGicV2EndOfInterrupt (
 270   IN UINTN                  GicInterruptInterfaceBase,
 271   IN UINTN                  Source
 272   );
 273
 274 //
 275 // GIC revision 3 specific declarations
 276 //
 277
 278 #define ICC_SRE_EL2_SRE         (1 << 0)
 279
 280 #define ARM_GICD_IROUTER_IRM BIT31
 281
 282 UINT32
 283 EFIAPI
 284 ArmGicV3GetControlSystemRegisterEnable (
 285   VOID
 286   );
 287
 288 VOID
 289 EFIAPI
 290 ArmGicV3SetControlSystemRegisterEnable (
 291   IN UINT32         ControlSystemRegisterEnable
 292   );
 293
 294 VOID
 295 EFIAPI
 296 ArmGicV3EnableInterruptInterface (
 297   VOID
 298   );
 299
 300 VOID
 301 EFIAPI
 302 ArmGicV3DisableInterruptInterface (
 303   VOID
 304   );
 305
 306 UINTN
 307 EFIAPI
 308 ArmGicV3AcknowledgeInterrupt (
 309   VOID
 310   );
 311
 312 VOID
 313 EFIAPI
 314 ArmGicV3EndOfInterrupt (
 315   IN UINTN                  Source
 316   );
 317
 318 VOID
 319 ArmGicV3SetBinaryPointer (
 320   IN UINTN                  BinaryPoint
 321   );
 322
 323 VOID
 324 ArmGicV3SetPriorityMask (
 325   IN UINTN                  Priority
 326   );
 327
 328 #endif