ArmPkg/Include/Library/ArmLib.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
   5
   6   This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef __ARM_LIB__
  17 #define __ARM_LIB__
  18
  19 #include <Uefi/UefiBaseType.h>
  20
  21 #ifdef MDE_CPU_ARM
  22   #include <Chipset/ArmV7.h>
  23 #elif defined(MDE_CPU_AARCH64)
  24   #include <Chipset/AArch64.h>
  25 #else
  26  #error "Unknown chipset."
  27 #endif
  28
  29 #define EFI_MEMORY_CACHETYPE_MASK   (EFI_MEMORY_UC | EFI_MEMORY_WC | \
  30                                      EFI_MEMORY_WT | EFI_MEMORY_WB | \
  31                                      EFI_MEMORY_UCE)
  32
  33 /**
  34  * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
  35  *
  36  * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
  37  * be used in Secure World to distinguished Secure to Non-Secure memory.
  38  */
  39 typedef enum {
  40   ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,
  41   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,
  42   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
  43   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,
  44   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
  45   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,
  46   ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
  47   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
  48 } ARM_MEMORY_REGION_ATTRIBUTES;
  49
  50 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
  51
  52 typedef struct {
  53   EFI_PHYSICAL_ADDRESS          PhysicalBase;
  54   EFI_VIRTUAL_ADDRESS           VirtualBase;
  55   UINT64                        Length;
  56   ARM_MEMORY_REGION_ATTRIBUTES  Attributes;
  57 } ARM_MEMORY_REGION_DESCRIPTOR;
  58
  59 typedef VOID (*CACHE_OPERATION)(VOID);
  60 typedef VOID (*LINE_OPERATION)(UINTN);
  61
  62 //
  63 // ARM Processor Mode
  64 //
  65 typedef enum {
  66   ARM_PROCESSOR_MODE_USER       = 0x10,
  67   ARM_PROCESSOR_MODE_FIQ        = 0x11,
  68   ARM_PROCESSOR_MODE_IRQ        = 0x12,
  69   ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
  70   ARM_PROCESSOR_MODE_ABORT      = 0x17,
  71   ARM_PROCESSOR_MODE_HYP        = 0x1A,
  72   ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,
  73   ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,
  74   ARM_PROCESSOR_MODE_MASK       = 0x1F
  75 } ARM_PROCESSOR_MODE;
  76
  77 //
  78 // ARM Cpu IDs
  79 //
  80 #define ARM_CPU_IMPLEMENTER_MASK          (0xFFU << 24)
  81 #define ARM_CPU_IMPLEMENTER_ARMLTD        (0x41U << 24)
  82 #define ARM_CPU_IMPLEMENTER_DEC           (0x44U << 24)
  83 #define ARM_CPU_IMPLEMENTER_MOT           (0x4DU << 24)
  84 #define ARM_CPU_IMPLEMENTER_QUALCOMM      (0x51U << 24)
  85 #define ARM_CPU_IMPLEMENTER_MARVELL       (0x56U << 24)
  86
  87 #define ARM_CPU_PRIMARY_PART_MASK         (0xFFF << 4)
  88 #define ARM_CPU_PRIMARY_PART_CORTEXA5     (0xC05 << 4)
  89 #define ARM_CPU_PRIMARY_PART_CORTEXA7     (0xC07 << 4)
  90 #define ARM_CPU_PRIMARY_PART_CORTEXA8     (0xC08 << 4)
  91 #define ARM_CPU_PRIMARY_PART_CORTEXA9     (0xC09 << 4)
  92 #define ARM_CPU_PRIMARY_PART_CORTEXA15    (0xC0F << 4)
  93
  94 //
  95 // ARM MP Core IDs
  96 //
  97 #define ARM_CORE_AFF0         0xFF
  98 #define ARM_CORE_AFF1         (0xFF << 8)
  99 #define ARM_CORE_AFF2         (0xFF << 16)
 100 #define ARM_CORE_AFF3         (0xFFULL << 32)
 101
 102 #define ARM_CORE_MASK         ARM_CORE_AFF0
 103 #define ARM_CLUSTER_MASK      ARM_CORE_AFF1
 104 #define GET_CORE_ID(MpId)     ((MpId) & ARM_CORE_MASK)
 105 #define GET_CLUSTER_ID(MpId)  (((MpId) & ARM_CLUSTER_MASK) >> 8)
 106 #define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))
 107 #define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
 108
 109 UINTN
 110 EFIAPI
 111 ArmDataCacheLineLength (
 112   VOID
 113   );
 114
 115 UINTN
 116 EFIAPI
 117 ArmInstructionCacheLineLength (
 118   VOID
 119   );
 120
 121 UINTN
 122 EFIAPI
 123 ArmCacheWritebackGranule (
 124   VOID
 125   );
 126
 127 UINTN
 128 EFIAPI
 129 ArmIsArchTimerImplemented (
 130   VOID
 131   );
 132
 133 UINTN
 134 EFIAPI
 135 ArmReadIdPfr0 (
 136   VOID
 137   );
 138
 139 UINTN
 140 EFIAPI
 141 ArmReadIdPfr1 (
 142   VOID
 143   );
 144
 145 UINTN
 146 EFIAPI
 147 ArmCacheInfo (
 148   VOID
 149   );
 150
 151 BOOLEAN
 152 EFIAPI
 153 ArmIsMpCore (
 154   VOID
 155   );
 156
 157 VOID
 158 EFIAPI
 159 ArmInvalidateDataCache (
 160   VOID
 161   );
 162
 163
 164 VOID
 165 EFIAPI
 166 ArmCleanInvalidateDataCache (
 167   VOID
 168   );
 169
 170 VOID
 171 EFIAPI
 172 ArmCleanDataCache (
 173   VOID
 174   );
 175
 176 VOID
 177 EFIAPI
 178 ArmInvalidateInstructionCache (
 179   VOID
 180   );
 181
 182 VOID
 183 EFIAPI
 184 ArmInvalidateDataCacheEntryByMVA (
 185   IN  UINTN   Address
 186   );
 187
 188 VOID
 189 EFIAPI
 190 ArmCleanDataCacheEntryToPoUByMVA (
 191   IN  UINTN   Address
 192   );
 193
 194 VOID
 195 EFIAPI
 196 ArmInvalidateInstructionCacheEntryToPoUByMVA (
 197   IN  UINTN   Address
 198   );
 199
 200 VOID
 201 EFIAPI
 202 ArmCleanDataCacheEntryByMVA (
 203 IN  UINTN   Address
 204 );
 205
 206 VOID
 207 EFIAPI
 208 ArmCleanInvalidateDataCacheEntryByMVA (
 209   IN  UINTN   Address
 210   );
 211
 212 VOID
 213 EFIAPI
 214 ArmInvalidateDataCacheEntryBySetWay (
 215   IN  UINTN  SetWayFormat
 216   );
 217
 218 VOID
 219 EFIAPI
 220 ArmCleanDataCacheEntryBySetWay (
 221   IN  UINTN  SetWayFormat
 222   );
 223
 224 VOID
 225 EFIAPI
 226 ArmCleanInvalidateDataCacheEntryBySetWay (
 227   IN  UINTN   SetWayFormat
 228   );
 229
 230 VOID
 231 EFIAPI
 232 ArmEnableDataCache (
 233   VOID
 234   );
 235
 236 VOID
 237 EFIAPI
 238 ArmDisableDataCache (
 239   VOID
 240   );
 241
 242 VOID
 243 EFIAPI
 244 ArmEnableInstructionCache (
 245   VOID
 246   );
 247
 248 VOID
 249 EFIAPI
 250 ArmDisableInstructionCache (
 251   VOID
 252   );
 253
 254 VOID
 255 EFIAPI
 256 ArmEnableMmu (
 257   VOID
 258   );
 259
 260 VOID
 261 EFIAPI
 262 ArmDisableMmu (
 263   VOID
 264   );
 265
 266 VOID
 267 EFIAPI
 268 ArmEnableCachesAndMmu (
 269   VOID
 270   );
 271
 272 VOID
 273 EFIAPI
 274 ArmDisableCachesAndMmu (
 275   VOID
 276   );
 277
 278 VOID
 279 EFIAPI
 280 ArmEnableInterrupts (
 281   VOID
 282   );
 283
 284 UINTN
 285 EFIAPI
 286 ArmDisableInterrupts (
 287   VOID
 288   );
 289
 290 BOOLEAN
 291 EFIAPI
 292 ArmGetInterruptState (
 293   VOID
 294   );
 295
 296 VOID
 297 EFIAPI
 298 ArmEnableAsynchronousAbort (
 299   VOID
 300   );
 301
 302 UINTN
 303 EFIAPI
 304 ArmDisableAsynchronousAbort (
 305   VOID
 306   );
 307
 308 VOID
 309 EFIAPI
 310 ArmEnableIrq (
 311   VOID
 312   );
 313
 314 UINTN
 315 EFIAPI
 316 ArmDisableIrq (
 317   VOID
 318   );
 319
 320 VOID
 321 EFIAPI
 322 ArmEnableFiq (
 323   VOID
 324   );
 325
 326 UINTN
 327 EFIAPI
 328 ArmDisableFiq (
 329   VOID
 330   );
 331
 332 BOOLEAN
 333 EFIAPI
 334 ArmGetFiqState (
 335   VOID
 336   );
 337
 338 /**
 339  * Invalidate Data and Instruction TLBs
 340  */
 341 VOID
 342 EFIAPI
 343 ArmInvalidateTlb (
 344   VOID
 345   );
 346
 347 VOID
 348 EFIAPI
 349 ArmUpdateTranslationTableEntry (
 350   IN  VOID     *TranslationTableEntry,
 351   IN  VOID     *Mva
 352   );
 353
 354 VOID
 355 EFIAPI
 356 ArmSetDomainAccessControl (
 357   IN  UINT32  Domain
 358   );
 359
 360 VOID
 361 EFIAPI
 362 ArmSetTTBR0 (
 363   IN  VOID  *TranslationTableBase
 364   );
 365
 366 VOID
 367 EFIAPI
 368 ArmSetTTBCR (
 369   IN  UINT32 Bits
 370   );
 371
 372 VOID *
 373 EFIAPI
 374 ArmGetTTBR0BaseAddress (
 375   VOID
 376   );
 377
 378 BOOLEAN
 379 EFIAPI
 380 ArmMmuEnabled (
 381   VOID
 382   );
 383
 384 VOID
 385 EFIAPI
 386 ArmEnableBranchPrediction (
 387   VOID
 388   );
 389
 390 VOID
 391 EFIAPI
 392 ArmDisableBranchPrediction (
 393   VOID
 394   );
 395
 396 VOID
 397 EFIAPI
 398 ArmSetLowVectors (
 399   VOID
 400   );
 401
 402 VOID
 403 EFIAPI
 404 ArmSetHighVectors (
 405   VOID
 406   );
 407
 408 VOID
 409 EFIAPI
 410 ArmDataMemoryBarrier (
 411   VOID
 412   );
 413
 414 VOID
 415 EFIAPI
 416 ArmDataSynchronizationBarrier (
 417   VOID
 418   );
 419
 420 VOID
 421 EFIAPI
 422 ArmInstructionSynchronizationBarrier (
 423   VOID
 424   );
 425
 426 VOID
 427 EFIAPI
 428 ArmWriteVBar (
 429   IN  UINTN   VectorBase
 430   );
 431
 432 UINTN
 433 EFIAPI
 434 ArmReadVBar (
 435   VOID
 436   );
 437
 438 VOID
 439 EFIAPI
 440 ArmWriteAuxCr (
 441   IN  UINT32    Bit
 442   );
 443
 444 UINT32
 445 EFIAPI
 446 ArmReadAuxCr (
 447   VOID
 448   );
 449
 450 VOID
 451 EFIAPI
 452 ArmSetAuxCrBit (
 453   IN  UINT32    Bits
 454   );
 455
 456 VOID
 457 EFIAPI
 458 ArmUnsetAuxCrBit (
 459   IN  UINT32    Bits
 460   );
 461
 462 VOID
 463 EFIAPI
 464 ArmCallSEV (
 465   VOID
 466   );
 467
 468 VOID
 469 EFIAPI
 470 ArmCallWFE (
 471   VOID
 472   );
 473
 474 VOID
 475 EFIAPI
 476 ArmCallWFI (
 477
 478   VOID
 479   );
 480
 481 UINTN
 482 EFIAPI
 483 ArmReadMpidr (
 484   VOID
 485   );
 486
 487 UINTN
 488 EFIAPI
 489 ArmReadMidr (
 490   VOID
 491   );
 492
 493 UINT32
 494 EFIAPI
 495 ArmReadCpacr (
 496   VOID
 497   );
 498
 499 VOID
 500 EFIAPI
 501 ArmWriteCpacr (
 502   IN  UINT32   Access
 503   );
 504
 505 VOID
 506 EFIAPI
 507 ArmEnableVFP (
 508   VOID
 509   );
 510
 511 /**
 512   Get the Secure Configuration Register value
 513
 514   @return   Value read from the Secure Configuration Register
 515
 516 **/
 517 UINT32
 518 EFIAPI
 519 ArmReadScr (
 520   VOID
 521   );
 522
 523 /**
 524   Set the Secure Configuration Register
 525
 526   @param Value   Value to write to the Secure Configuration Register
 527
 528 **/
 529 VOID
 530 EFIAPI
 531 ArmWriteScr (
 532   IN  UINT32   Value
 533   );
 534
 535 UINT32
 536 EFIAPI
 537 ArmReadMVBar (
 538   VOID
 539   );
 540
 541 VOID
 542 EFIAPI
 543 ArmWriteMVBar (
 544   IN  UINT32   VectorMonitorBase
 545   );
 546
 547 UINT32
 548 EFIAPI
 549 ArmReadSctlr (
 550   VOID
 551   );
 552
 553 UINTN
 554 EFIAPI
 555 ArmReadHVBar (
 556   VOID
 557   );
 558
 559 VOID
 560 EFIAPI
 561 ArmWriteHVBar (
 562   IN  UINTN   HypModeVectorBase
 563   );
 564
 565
 566 //
 567 // Helper functions for accessing CPU ACTLR
 568 //
 569
 570 UINTN
 571 EFIAPI
 572 ArmReadCpuActlr (
 573   VOID
 574   );
 575
 576 VOID
 577 EFIAPI
 578 ArmWriteCpuActlr (
 579   IN  UINTN Val
 580   );
 581
 582 VOID
 583 EFIAPI
 584 ArmSetCpuActlrBit (
 585   IN  UINTN    Bits
 586   );
 587
 588 VOID
 589 EFIAPI
 590 ArmUnsetCpuActlrBit (
 591   IN  UINTN    Bits
 592   );
 593
 594 //
 595 // Accessors for the architected generic timer registers
 596 //
 597
 598 #define ARM_ARCH_TIMER_ENABLE           (1 << 0)
 599 #define ARM_ARCH_TIMER_IMASK            (1 << 1)
 600 #define ARM_ARCH_TIMER_ISTATUS          (1 << 2)
 601
 602 UINTN
 603 EFIAPI
 604 ArmReadCntFrq (
 605   VOID
 606   );
 607
 608 VOID
 609 EFIAPI
 610 ArmWriteCntFrq (
 611   UINTN   FreqInHz
 612   );
 613
 614 UINT64
 615 EFIAPI
 616 ArmReadCntPct (
 617   VOID
 618   );
 619
 620 UINTN
 621 EFIAPI
 622 ArmReadCntkCtl (
 623   VOID
 624   );
 625
 626 VOID
 627 EFIAPI
 628 ArmWriteCntkCtl (
 629   UINTN   Val
 630   );
 631
 632 UINTN
 633 EFIAPI
 634 ArmReadCntpTval (
 635   VOID
 636   );
 637
 638 VOID
 639 EFIAPI
 640 ArmWriteCntpTval (
 641   UINTN   Val
 642   );
 643
 644 UINTN
 645 EFIAPI
 646 ArmReadCntpCtl (
 647   VOID
 648   );
 649
 650 VOID
 651 EFIAPI
 652 ArmWriteCntpCtl (
 653   UINTN   Val
 654   );
 655
 656 UINTN
 657 EFIAPI
 658 ArmReadCntvTval (
 659   VOID
 660   );
 661
 662 VOID
 663 EFIAPI
 664 ArmWriteCntvTval (
 665   UINTN   Val
 666   );
 667
 668 UINTN
 669 EFIAPI
 670 ArmReadCntvCtl (
 671   VOID
 672   );
 673
 674 VOID
 675 EFIAPI
 676 ArmWriteCntvCtl (
 677   UINTN   Val
 678   );
 679
 680 UINT64
 681 EFIAPI
 682 ArmReadCntvCt (
 683   VOID
 684   );
 685
 686 UINT64
 687 EFIAPI
 688 ArmReadCntpCval (
 689   VOID
 690   );
 691
 692 VOID
 693 EFIAPI
 694 ArmWriteCntpCval (
 695   UINT64   Val
 696   );
 697
 698 UINT64
 699 EFIAPI
 700 ArmReadCntvCval (
 701   VOID
 702   );
 703
 704 VOID
 705 EFIAPI
 706 ArmWriteCntvCval (
 707   UINT64   Val
 708   );
 709
 710 UINT64
 711 EFIAPI
 712 ArmReadCntvOff (
 713   VOID
 714   );
 715
 716 VOID
 717 EFIAPI
 718 ArmWriteCntvOff (
 719   UINT64   Val
 720   );
 721
 722 #endif // __ARM_LIB__