3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
4 Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 #include <Uefi/UefiBaseType.h>
22 #include <Chipset/ArmV7.h>
23 #elif defined(MDE_CPU_AARCH64)
24 #include <Chipset/AArch64.h>
26 #error "Unknown chipset."
29 #define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \
30 EFI_MEMORY_WT | EFI_MEMORY_WB | \
34 * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
36 * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
37 * be used in Secure World to distinguished Secure to Non-Secure memory.
40 ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
= 0,
41 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED
,
42 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
,
43 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK
,
44 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH
,
45 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH
,
46 ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
,
47 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
48 } ARM_MEMORY_REGION_ATTRIBUTES
;
50 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
53 EFI_PHYSICAL_ADDRESS PhysicalBase
;
54 EFI_VIRTUAL_ADDRESS VirtualBase
;
56 ARM_MEMORY_REGION_ATTRIBUTES Attributes
;
57 } ARM_MEMORY_REGION_DESCRIPTOR
;
59 typedef VOID (*CACHE_OPERATION
)(VOID
);
60 typedef VOID (*LINE_OPERATION
)(UINTN
);
66 ARM_PROCESSOR_MODE_USER
= 0x10,
67 ARM_PROCESSOR_MODE_FIQ
= 0x11,
68 ARM_PROCESSOR_MODE_IRQ
= 0x12,
69 ARM_PROCESSOR_MODE_SUPERVISOR
= 0x13,
70 ARM_PROCESSOR_MODE_ABORT
= 0x17,
71 ARM_PROCESSOR_MODE_HYP
= 0x1A,
72 ARM_PROCESSOR_MODE_UNDEFINED
= 0x1B,
73 ARM_PROCESSOR_MODE_SYSTEM
= 0x1F,
74 ARM_PROCESSOR_MODE_MASK
= 0x1F
80 #define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)
81 #define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)
82 #define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)
83 #define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)
84 #define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)
85 #define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)
87 #define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)
88 #define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)
89 #define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)
90 #define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)
91 #define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)
92 #define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)
97 #define ARM_CORE_AFF0 0xFF
98 #define ARM_CORE_AFF1 (0xFF << 8)
99 #define ARM_CORE_AFF2 (0xFF << 16)
100 #define ARM_CORE_AFF3 (0xFFULL << 32)
102 #define ARM_CORE_MASK ARM_CORE_AFF0
103 #define ARM_CLUSTER_MASK ARM_CORE_AFF1
104 #define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
105 #define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
106 #define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
107 #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
111 ArmDataCacheLineLength (
117 ArmInstructionCacheLineLength (
123 ArmCacheWritebackGranule (
129 ArmIsArchTimerImplemented (
159 ArmInvalidateDataCache (
166 ArmCleanInvalidateDataCache (
178 ArmInvalidateInstructionCache (
184 ArmInvalidateDataCacheEntryByMVA (
190 ArmCleanDataCacheEntryToPoUByMVA (
196 ArmInvalidateInstructionCacheEntryToPoUByMVA (
202 ArmCleanDataCacheEntryByMVA (
208 ArmCleanInvalidateDataCacheEntryByMVA (
214 ArmInvalidateDataCacheEntryBySetWay (
215 IN UINTN SetWayFormat
220 ArmCleanDataCacheEntryBySetWay (
221 IN UINTN SetWayFormat
226 ArmCleanInvalidateDataCacheEntryBySetWay (
227 IN UINTN SetWayFormat
238 ArmDisableDataCache (
244 ArmEnableInstructionCache (
250 ArmDisableInstructionCache (
268 ArmEnableCachesAndMmu (
274 ArmDisableCachesAndMmu (
280 ArmEnableInterrupts (
286 ArmDisableInterrupts (
292 ArmGetInterruptState (
298 ArmEnableAsynchronousAbort (
304 ArmDisableAsynchronousAbort (
339 * Invalidate Data and Instruction TLBs
349 ArmUpdateTranslationTableEntry (
350 IN VOID
*TranslationTableEntry
,
356 ArmSetDomainAccessControl (
363 IN VOID
*TranslationTableBase
374 ArmGetTTBR0BaseAddress (
386 ArmEnableBranchPrediction (
392 ArmDisableBranchPrediction (
410 ArmDataMemoryBarrier (
416 ArmDataSynchronizationBarrier (
422 ArmInstructionSynchronizationBarrier (
512 Get the Secure Configuration Register value
514 @return Value read from the Secure Configuration Register
524 Set the Secure Configuration Register
526 @param Value Value to write to the Secure Configuration Register
544 IN UINT32 VectorMonitorBase
562 IN UINTN HypModeVectorBase
567 // Helper functions for accessing CPU ACTLR
590 ArmUnsetCpuActlrBit (
595 // Accessors for the architected generic timer registers
598 #define ARM_ARCH_TIMER_ENABLE (1 << 0)
599 #define ARM_ARCH_TIMER_IMASK (1 << 1)
600 #define ARM_ARCH_TIMER_ISTATUS (1 << 2)
722 #endif // __ARM_LIB__