ArmPkg/Include/Library/ArmLib.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
   5   Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>
   6
   7   SPDX-License-Identifier: BSD-2-Clause-Patent
   8
   9 **/
  10
  11 #ifndef __ARM_LIB__
  12 #define __ARM_LIB__
  13
  14 #include <Uefi/UefiBaseType.h>
  15
  16 #ifdef MDE_CPU_ARM
  17   #include <Chipset/ArmV7.h>
  18 #elif defined(MDE_CPU_AARCH64)
  19   #include <Chipset/AArch64.h>
  20 #else
  21  #error "Unknown chipset."
  22 #endif
  23
  24 #define EFI_MEMORY_CACHETYPE_MASK   (EFI_MEMORY_UC | EFI_MEMORY_WC | \
  25                                      EFI_MEMORY_WT | EFI_MEMORY_WB | \
  26                                      EFI_MEMORY_UCE)
  27
  28 /**
  29  * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
  30  *
  31  * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
  32  * be used in Secure World to distinguished Secure to Non-Secure memory.
  33  */
  34 typedef enum {
  35   ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,
  36   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,
  37   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
  38   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,
  39
  40   // On some platforms, memory mapped flash region is designed as not supporting
  41   // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special
  42   // need.
  43   // Do NOT use below two attributes if you are not sure.
  44   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,
  45   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,
  46
  47   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
  48   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,
  49   ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
  50   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
  51 } ARM_MEMORY_REGION_ATTRIBUTES;
  52
  53 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
  54
  55 typedef struct {
  56   EFI_PHYSICAL_ADDRESS          PhysicalBase;
  57   EFI_VIRTUAL_ADDRESS           VirtualBase;
  58   UINT64                        Length;
  59   ARM_MEMORY_REGION_ATTRIBUTES  Attributes;
  60 } ARM_MEMORY_REGION_DESCRIPTOR;
  61
  62 typedef VOID (*CACHE_OPERATION)(VOID);
  63 typedef VOID (*LINE_OPERATION)(UINTN);
  64
  65 //
  66 // ARM Processor Mode
  67 //
  68 typedef enum {
  69   ARM_PROCESSOR_MODE_USER       = 0x10,
  70   ARM_PROCESSOR_MODE_FIQ        = 0x11,
  71   ARM_PROCESSOR_MODE_IRQ        = 0x12,
  72   ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
  73   ARM_PROCESSOR_MODE_ABORT      = 0x17,
  74   ARM_PROCESSOR_MODE_HYP        = 0x1A,
  75   ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,
  76   ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,
  77   ARM_PROCESSOR_MODE_MASK       = 0x1F
  78 } ARM_PROCESSOR_MODE;
  79
  80 //
  81 // ARM Cpu IDs
  82 //
  83 #define ARM_CPU_IMPLEMENTER_MASK          (0xFFU << 24)
  84 #define ARM_CPU_IMPLEMENTER_ARMLTD        (0x41U << 24)
  85 #define ARM_CPU_IMPLEMENTER_DEC           (0x44U << 24)
  86 #define ARM_CPU_IMPLEMENTER_MOT           (0x4DU << 24)
  87 #define ARM_CPU_IMPLEMENTER_QUALCOMM      (0x51U << 24)
  88 #define ARM_CPU_IMPLEMENTER_MARVELL       (0x56U << 24)
  89
  90 #define ARM_CPU_PRIMARY_PART_MASK         (0xFFF << 4)
  91 #define ARM_CPU_PRIMARY_PART_CORTEXA5     (0xC05 << 4)
  92 #define ARM_CPU_PRIMARY_PART_CORTEXA7     (0xC07 << 4)
  93 #define ARM_CPU_PRIMARY_PART_CORTEXA8     (0xC08 << 4)
  94 #define ARM_CPU_PRIMARY_PART_CORTEXA9     (0xC09 << 4)
  95 #define ARM_CPU_PRIMARY_PART_CORTEXA15    (0xC0F << 4)
  96
  97 //
  98 // ARM MP Core IDs
  99 //
 100 #define ARM_CORE_AFF0         0xFF
 101 #define ARM_CORE_AFF1         (0xFF << 8)
 102 #define ARM_CORE_AFF2         (0xFF << 16)
 103 #define ARM_CORE_AFF3         (0xFFULL << 32)
 104
 105 #define ARM_CORE_MASK         ARM_CORE_AFF0
 106 #define ARM_CLUSTER_MASK      ARM_CORE_AFF1
 107 #define GET_CORE_ID(MpId)     ((MpId) & ARM_CORE_MASK)
 108 #define GET_CLUSTER_ID(MpId)  (((MpId) & ARM_CLUSTER_MASK) >> 8)
 109 #define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))
 110 #define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
 111
 112 UINTN
 113 EFIAPI
 114 ArmDataCacheLineLength (
 115   VOID
 116   );
 117
 118 UINTN
 119 EFIAPI
 120 ArmInstructionCacheLineLength (
 121   VOID
 122   );
 123
 124 UINTN
 125 EFIAPI
 126 ArmCacheWritebackGranule (
 127   VOID
 128   );
 129
 130 UINTN
 131 EFIAPI
 132 ArmIsArchTimerImplemented (
 133   VOID
 134   );
 135
 136 UINTN
 137 EFIAPI
 138 ArmCacheInfo (
 139   VOID
 140   );
 141
 142 BOOLEAN
 143 EFIAPI
 144 ArmIsMpCore (
 145   VOID
 146   );
 147
 148 VOID
 149 EFIAPI
 150 ArmInvalidateDataCache (
 151   VOID
 152   );
 153
 154
 155 VOID
 156 EFIAPI
 157 ArmCleanInvalidateDataCache (
 158   VOID
 159   );
 160
 161 VOID
 162 EFIAPI
 163 ArmCleanDataCache (
 164   VOID
 165   );
 166
 167 VOID
 168 EFIAPI
 169 ArmInvalidateInstructionCache (
 170   VOID
 171   );
 172
 173 VOID
 174 EFIAPI
 175 ArmInvalidateDataCacheEntryByMVA (
 176   IN  UINTN   Address
 177   );
 178
 179 VOID
 180 EFIAPI
 181 ArmCleanDataCacheEntryToPoUByMVA (
 182   IN  UINTN   Address
 183   );
 184
 185 VOID
 186 EFIAPI
 187 ArmInvalidateInstructionCacheEntryToPoUByMVA (
 188   IN  UINTN   Address
 189   );
 190
 191 VOID
 192 EFIAPI
 193 ArmCleanDataCacheEntryByMVA (
 194 IN  UINTN   Address
 195 );
 196
 197 VOID
 198 EFIAPI
 199 ArmCleanInvalidateDataCacheEntryByMVA (
 200   IN  UINTN   Address
 201   );
 202
 203 VOID
 204 EFIAPI
 205 ArmEnableDataCache (
 206   VOID
 207   );
 208
 209 VOID
 210 EFIAPI
 211 ArmDisableDataCache (
 212   VOID
 213   );
 214
 215 VOID
 216 EFIAPI
 217 ArmEnableInstructionCache (
 218   VOID
 219   );
 220
 221 VOID
 222 EFIAPI
 223 ArmDisableInstructionCache (
 224   VOID
 225   );
 226
 227 VOID
 228 EFIAPI
 229 ArmEnableMmu (
 230   VOID
 231   );
 232
 233 VOID
 234 EFIAPI
 235 ArmDisableMmu (
 236   VOID
 237   );
 238
 239 VOID
 240 EFIAPI
 241 ArmEnableCachesAndMmu (
 242   VOID
 243   );
 244
 245 VOID
 246 EFIAPI
 247 ArmDisableCachesAndMmu (
 248   VOID
 249   );
 250
 251 VOID
 252 EFIAPI
 253 ArmEnableInterrupts (
 254   VOID
 255   );
 256
 257 UINTN
 258 EFIAPI
 259 ArmDisableInterrupts (
 260   VOID
 261   );
 262
 263 BOOLEAN
 264 EFIAPI
 265 ArmGetInterruptState (
 266   VOID
 267   );
 268
 269 VOID
 270 EFIAPI
 271 ArmEnableAsynchronousAbort (
 272   VOID
 273   );
 274
 275 UINTN
 276 EFIAPI
 277 ArmDisableAsynchronousAbort (
 278   VOID
 279   );
 280
 281 VOID
 282 EFIAPI
 283 ArmEnableIrq (
 284   VOID
 285   );
 286
 287 UINTN
 288 EFIAPI
 289 ArmDisableIrq (
 290   VOID
 291   );
 292
 293 VOID
 294 EFIAPI
 295 ArmEnableFiq (
 296   VOID
 297   );
 298
 299 UINTN
 300 EFIAPI
 301 ArmDisableFiq (
 302   VOID
 303   );
 304
 305 BOOLEAN
 306 EFIAPI
 307 ArmGetFiqState (
 308   VOID
 309   );
 310
 311 /**
 312  * Invalidate Data and Instruction TLBs
 313  */
 314 VOID
 315 EFIAPI
 316 ArmInvalidateTlb (
 317   VOID
 318   );
 319
 320 VOID
 321 EFIAPI
 322 ArmUpdateTranslationTableEntry (
 323   IN  VOID     *TranslationTableEntry,
 324   IN  VOID     *Mva
 325   );
 326
 327 VOID
 328 EFIAPI
 329 ArmSetDomainAccessControl (
 330   IN  UINT32  Domain
 331   );
 332
 333 VOID
 334 EFIAPI
 335 ArmSetTTBR0 (
 336   IN  VOID  *TranslationTableBase
 337   );
 338
 339 VOID
 340 EFIAPI
 341 ArmSetTTBCR (
 342   IN  UINT32 Bits
 343   );
 344
 345 VOID *
 346 EFIAPI
 347 ArmGetTTBR0BaseAddress (
 348   VOID
 349   );
 350
 351 BOOLEAN
 352 EFIAPI
 353 ArmMmuEnabled (
 354   VOID
 355   );
 356
 357 VOID
 358 EFIAPI
 359 ArmEnableBranchPrediction (
 360   VOID
 361   );
 362
 363 VOID
 364 EFIAPI
 365 ArmDisableBranchPrediction (
 366   VOID
 367   );
 368
 369 VOID
 370 EFIAPI
 371 ArmSetLowVectors (
 372   VOID
 373   );
 374
 375 VOID
 376 EFIAPI
 377 ArmSetHighVectors (
 378   VOID
 379   );
 380
 381 VOID
 382 EFIAPI
 383 ArmDataMemoryBarrier (
 384   VOID
 385   );
 386
 387 VOID
 388 EFIAPI
 389 ArmDataSynchronizationBarrier (
 390   VOID
 391   );
 392
 393 VOID
 394 EFIAPI
 395 ArmInstructionSynchronizationBarrier (
 396   VOID
 397   );
 398
 399 VOID
 400 EFIAPI
 401 ArmWriteVBar (
 402   IN  UINTN   VectorBase
 403   );
 404
 405 UINTN
 406 EFIAPI
 407 ArmReadVBar (
 408   VOID
 409   );
 410
 411 VOID
 412 EFIAPI
 413 ArmWriteAuxCr (
 414   IN  UINT32    Bit
 415   );
 416
 417 UINT32
 418 EFIAPI
 419 ArmReadAuxCr (
 420   VOID
 421   );
 422
 423 VOID
 424 EFIAPI
 425 ArmSetAuxCrBit (
 426   IN  UINT32    Bits
 427   );
 428
 429 VOID
 430 EFIAPI
 431 ArmUnsetAuxCrBit (
 432   IN  UINT32    Bits
 433   );
 434
 435 VOID
 436 EFIAPI
 437 ArmCallSEV (
 438   VOID
 439   );
 440
 441 VOID
 442 EFIAPI
 443 ArmCallWFE (
 444   VOID
 445   );
 446
 447 VOID
 448 EFIAPI
 449 ArmCallWFI (
 450
 451   VOID
 452   );
 453
 454 UINTN
 455 EFIAPI
 456 ArmReadMpidr (
 457   VOID
 458   );
 459
 460 UINTN
 461 EFIAPI
 462 ArmReadMidr (
 463   VOID
 464   );
 465
 466 UINT32
 467 EFIAPI
 468 ArmReadCpacr (
 469   VOID
 470   );
 471
 472 VOID
 473 EFIAPI
 474 ArmWriteCpacr (
 475   IN  UINT32   Access
 476   );
 477
 478 VOID
 479 EFIAPI
 480 ArmEnableVFP (
 481   VOID
 482   );
 483
 484 /**
 485   Get the Secure Configuration Register value
 486
 487   @return   Value read from the Secure Configuration Register
 488
 489 **/
 490 UINT32
 491 EFIAPI
 492 ArmReadScr (
 493   VOID
 494   );
 495
 496 /**
 497   Set the Secure Configuration Register
 498
 499   @param Value   Value to write to the Secure Configuration Register
 500
 501 **/
 502 VOID
 503 EFIAPI
 504 ArmWriteScr (
 505   IN  UINT32   Value
 506   );
 507
 508 UINT32
 509 EFIAPI
 510 ArmReadMVBar (
 511   VOID
 512   );
 513
 514 VOID
 515 EFIAPI
 516 ArmWriteMVBar (
 517   IN  UINT32   VectorMonitorBase
 518   );
 519
 520 UINT32
 521 EFIAPI
 522 ArmReadSctlr (
 523   VOID
 524   );
 525
 526 VOID
 527 EFIAPI
 528 ArmWriteSctlr (
 529   IN  UINT32   Value
 530   );
 531
 532 UINTN
 533 EFIAPI
 534 ArmReadHVBar (
 535   VOID
 536   );
 537
 538 VOID
 539 EFIAPI
 540 ArmWriteHVBar (
 541   IN  UINTN   HypModeVectorBase
 542   );
 543
 544
 545 //
 546 // Helper functions for accessing CPU ACTLR
 547 //
 548
 549 UINTN
 550 EFIAPI
 551 ArmReadCpuActlr (
 552   VOID
 553   );
 554
 555 VOID
 556 EFIAPI
 557 ArmWriteCpuActlr (
 558   IN  UINTN Val
 559   );
 560
 561 VOID
 562 EFIAPI
 563 ArmSetCpuActlrBit (
 564   IN  UINTN    Bits
 565   );
 566
 567 VOID
 568 EFIAPI
 569 ArmUnsetCpuActlrBit (
 570   IN  UINTN    Bits
 571   );
 572
 573 //
 574 // Accessors for the architected generic timer registers
 575 //
 576
 577 #define ARM_ARCH_TIMER_ENABLE           (1 << 0)
 578 #define ARM_ARCH_TIMER_IMASK            (1 << 1)
 579 #define ARM_ARCH_TIMER_ISTATUS          (1 << 2)
 580
 581 UINTN
 582 EFIAPI
 583 ArmReadCntFrq (
 584   VOID
 585   );
 586
 587 VOID
 588 EFIAPI
 589 ArmWriteCntFrq (
 590   UINTN   FreqInHz
 591   );
 592
 593 UINT64
 594 EFIAPI
 595 ArmReadCntPct (
 596   VOID
 597   );
 598
 599 UINTN
 600 EFIAPI
 601 ArmReadCntkCtl (
 602   VOID
 603   );
 604
 605 VOID
 606 EFIAPI
 607 ArmWriteCntkCtl (
 608   UINTN   Val
 609   );
 610
 611 UINTN
 612 EFIAPI
 613 ArmReadCntpTval (
 614   VOID
 615   );
 616
 617 VOID
 618 EFIAPI
 619 ArmWriteCntpTval (
 620   UINTN   Val
 621   );
 622
 623 UINTN
 624 EFIAPI
 625 ArmReadCntpCtl (
 626   VOID
 627   );
 628
 629 VOID
 630 EFIAPI
 631 ArmWriteCntpCtl (
 632   UINTN   Val
 633   );
 634
 635 UINTN
 636 EFIAPI
 637 ArmReadCntvTval (
 638   VOID
 639   );
 640
 641 VOID
 642 EFIAPI
 643 ArmWriteCntvTval (
 644   UINTN   Val
 645   );
 646
 647 UINTN
 648 EFIAPI
 649 ArmReadCntvCtl (
 650   VOID
 651   );
 652
 653 VOID
 654 EFIAPI
 655 ArmWriteCntvCtl (
 656   UINTN   Val
 657   );
 658
 659 UINT64
 660 EFIAPI
 661 ArmReadCntvCt (
 662   VOID
 663   );
 664
 665 UINT64
 666 EFIAPI
 667 ArmReadCntpCval (
 668   VOID
 669   );
 670
 671 VOID
 672 EFIAPI
 673 ArmWriteCntpCval (
 674   UINT64   Val
 675   );
 676
 677 UINT64
 678 EFIAPI
 679 ArmReadCntvCval (
 680   VOID
 681   );
 682
 683 VOID
 684 EFIAPI
 685 ArmWriteCntvCval (
 686   UINT64   Val
 687   );
 688
 689 UINT64
 690 EFIAPI
 691 ArmReadCntvOff (
 692   VOID
 693   );
 694
 695 VOID
 696 EFIAPI
 697 ArmWriteCntvOff (
 698   UINT64   Val
 699   );
 700
 701 UINTN
 702 EFIAPI
 703 ArmGetPhysicalAddressBits (
 704   VOID
 705   );
 706
 707
 708 ///
 709 ///  ID Register Helper functions
 710 ///
 711
 712 /**
 713   Check whether the CPU supports the GIC system register interface (any version)
 714
 715   @return   Whether GIC System Register Interface is supported
 716
 717 **/
 718 BOOLEAN
 719 EFIAPI
 720 ArmHasGicSystemRegisters (
 721   VOID
 722   );
 723
 724 #ifdef MDE_CPU_ARM
 725 ///
 726 /// AArch32-only ID Register Helper functions
 727 ///
 728 /**
 729   Check whether the CPU supports the Security extensions
 730
 731   @return   Whether the Security extensions are implemented
 732
 733 **/
 734 BOOLEAN
 735 EFIAPI
 736 ArmHasSecurityExtensions (
 737   VOID
 738   );
 739 #endif // MDE_CPU_ARM
 740
 741 #endif // __ARM_LIB__