ArmPkg/Include/Library/ArmLib.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
   5
   6   SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9
  10 #ifndef __ARM_LIB__
  11 #define __ARM_LIB__
  12
  13 #include <Uefi/UefiBaseType.h>
  14
  15 #ifdef MDE_CPU_ARM
  16   #include <Chipset/ArmV7.h>
  17 #elif defined(MDE_CPU_AARCH64)
  18   #include <Chipset/AArch64.h>
  19 #else
  20  #error "Unknown chipset."
  21 #endif
  22
  23 #define EFI_MEMORY_CACHETYPE_MASK   (EFI_MEMORY_UC | EFI_MEMORY_WC | \
  24                                      EFI_MEMORY_WT | EFI_MEMORY_WB | \
  25                                      EFI_MEMORY_UCE)
  26
  27 /**
  28  * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
  29  *
  30  * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
  31  * be used in Secure World to distinguished Secure to Non-Secure memory.
  32  */
  33 typedef enum {
  34   ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,
  35   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,
  36   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
  37   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,
  38
  39   // On some platforms, memory mapped flash region is designed as not supporting
  40   // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special
  41   // need.
  42   // Do NOT use below two attributes if you are not sure.
  43   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,
  44   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,
  45
  46   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
  47   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,
  48   ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
  49   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
  50 } ARM_MEMORY_REGION_ATTRIBUTES;
  51
  52 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
  53
  54 typedef struct {
  55   EFI_PHYSICAL_ADDRESS          PhysicalBase;
  56   EFI_VIRTUAL_ADDRESS           VirtualBase;
  57   UINT64                        Length;
  58   ARM_MEMORY_REGION_ATTRIBUTES  Attributes;
  59 } ARM_MEMORY_REGION_DESCRIPTOR;
  60
  61 typedef VOID (*CACHE_OPERATION)(VOID);
  62 typedef VOID (*LINE_OPERATION)(UINTN);
  63
  64 //
  65 // ARM Processor Mode
  66 //
  67 typedef enum {
  68   ARM_PROCESSOR_MODE_USER       = 0x10,
  69   ARM_PROCESSOR_MODE_FIQ        = 0x11,
  70   ARM_PROCESSOR_MODE_IRQ        = 0x12,
  71   ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
  72   ARM_PROCESSOR_MODE_ABORT      = 0x17,
  73   ARM_PROCESSOR_MODE_HYP        = 0x1A,
  74   ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,
  75   ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,
  76   ARM_PROCESSOR_MODE_MASK       = 0x1F
  77 } ARM_PROCESSOR_MODE;
  78
  79 //
  80 // ARM Cpu IDs
  81 //
  82 #define ARM_CPU_IMPLEMENTER_MASK          (0xFFU << 24)
  83 #define ARM_CPU_IMPLEMENTER_ARMLTD        (0x41U << 24)
  84 #define ARM_CPU_IMPLEMENTER_DEC           (0x44U << 24)
  85 #define ARM_CPU_IMPLEMENTER_MOT           (0x4DU << 24)
  86 #define ARM_CPU_IMPLEMENTER_QUALCOMM      (0x51U << 24)
  87 #define ARM_CPU_IMPLEMENTER_MARVELL       (0x56U << 24)
  88
  89 #define ARM_CPU_PRIMARY_PART_MASK         (0xFFF << 4)
  90 #define ARM_CPU_PRIMARY_PART_CORTEXA5     (0xC05 << 4)
  91 #define ARM_CPU_PRIMARY_PART_CORTEXA7     (0xC07 << 4)
  92 #define ARM_CPU_PRIMARY_PART_CORTEXA8     (0xC08 << 4)
  93 #define ARM_CPU_PRIMARY_PART_CORTEXA9     (0xC09 << 4)
  94 #define ARM_CPU_PRIMARY_PART_CORTEXA15    (0xC0F << 4)
  95
  96 //
  97 // ARM MP Core IDs
  98 //
  99 #define ARM_CORE_AFF0         0xFF
 100 #define ARM_CORE_AFF1         (0xFF << 8)
 101 #define ARM_CORE_AFF2         (0xFF << 16)
 102 #define ARM_CORE_AFF3         (0xFFULL << 32)
 103
 104 #define ARM_CORE_MASK         ARM_CORE_AFF0
 105 #define ARM_CLUSTER_MASK      ARM_CORE_AFF1
 106 #define GET_CORE_ID(MpId)     ((MpId) & ARM_CORE_MASK)
 107 #define GET_CLUSTER_ID(MpId)  (((MpId) & ARM_CLUSTER_MASK) >> 8)
 108 #define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))
 109 #define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
 110
 111 UINTN
 112 EFIAPI
 113 ArmDataCacheLineLength (
 114   VOID
 115   );
 116
 117 UINTN
 118 EFIAPI
 119 ArmInstructionCacheLineLength (
 120   VOID
 121   );
 122
 123 UINTN
 124 EFIAPI
 125 ArmCacheWritebackGranule (
 126   VOID
 127   );
 128
 129 UINTN
 130 EFIAPI
 131 ArmIsArchTimerImplemented (
 132   VOID
 133   );
 134
 135 UINTN
 136 EFIAPI
 137 ArmReadIdPfr0 (
 138   VOID
 139   );
 140
 141 UINTN
 142 EFIAPI
 143 ArmReadIdPfr1 (
 144   VOID
 145   );
 146
 147 UINTN
 148 EFIAPI
 149 ArmCacheInfo (
 150   VOID
 151   );
 152
 153 BOOLEAN
 154 EFIAPI
 155 ArmIsMpCore (
 156   VOID
 157   );
 158
 159 VOID
 160 EFIAPI
 161 ArmInvalidateDataCache (
 162   VOID
 163   );
 164
 165
 166 VOID
 167 EFIAPI
 168 ArmCleanInvalidateDataCache (
 169   VOID
 170   );
 171
 172 VOID
 173 EFIAPI
 174 ArmCleanDataCache (
 175   VOID
 176   );
 177
 178 VOID
 179 EFIAPI
 180 ArmInvalidateInstructionCache (
 181   VOID
 182   );
 183
 184 VOID
 185 EFIAPI
 186 ArmInvalidateDataCacheEntryByMVA (
 187   IN  UINTN   Address
 188   );
 189
 190 VOID
 191 EFIAPI
 192 ArmCleanDataCacheEntryToPoUByMVA (
 193   IN  UINTN   Address
 194   );
 195
 196 VOID
 197 EFIAPI
 198 ArmInvalidateInstructionCacheEntryToPoUByMVA (
 199   IN  UINTN   Address
 200   );
 201
 202 VOID
 203 EFIAPI
 204 ArmCleanDataCacheEntryByMVA (
 205 IN  UINTN   Address
 206 );
 207
 208 VOID
 209 EFIAPI
 210 ArmCleanInvalidateDataCacheEntryByMVA (
 211   IN  UINTN   Address
 212   );
 213
 214 VOID
 215 EFIAPI
 216 ArmEnableDataCache (
 217   VOID
 218   );
 219
 220 VOID
 221 EFIAPI
 222 ArmDisableDataCache (
 223   VOID
 224   );
 225
 226 VOID
 227 EFIAPI
 228 ArmEnableInstructionCache (
 229   VOID
 230   );
 231
 232 VOID
 233 EFIAPI
 234 ArmDisableInstructionCache (
 235   VOID
 236   );
 237
 238 VOID
 239 EFIAPI
 240 ArmEnableMmu (
 241   VOID
 242   );
 243
 244 VOID
 245 EFIAPI
 246 ArmDisableMmu (
 247   VOID
 248   );
 249
 250 VOID
 251 EFIAPI
 252 ArmEnableCachesAndMmu (
 253   VOID
 254   );
 255
 256 VOID
 257 EFIAPI
 258 ArmDisableCachesAndMmu (
 259   VOID
 260   );
 261
 262 VOID
 263 EFIAPI
 264 ArmEnableInterrupts (
 265   VOID
 266   );
 267
 268 UINTN
 269 EFIAPI
 270 ArmDisableInterrupts (
 271   VOID
 272   );
 273
 274 BOOLEAN
 275 EFIAPI
 276 ArmGetInterruptState (
 277   VOID
 278   );
 279
 280 VOID
 281 EFIAPI
 282 ArmEnableAsynchronousAbort (
 283   VOID
 284   );
 285
 286 UINTN
 287 EFIAPI
 288 ArmDisableAsynchronousAbort (
 289   VOID
 290   );
 291
 292 VOID
 293 EFIAPI
 294 ArmEnableIrq (
 295   VOID
 296   );
 297
 298 UINTN
 299 EFIAPI
 300 ArmDisableIrq (
 301   VOID
 302   );
 303
 304 VOID
 305 EFIAPI
 306 ArmEnableFiq (
 307   VOID
 308   );
 309
 310 UINTN
 311 EFIAPI
 312 ArmDisableFiq (
 313   VOID
 314   );
 315
 316 BOOLEAN
 317 EFIAPI
 318 ArmGetFiqState (
 319   VOID
 320   );
 321
 322 /**
 323  * Invalidate Data and Instruction TLBs
 324  */
 325 VOID
 326 EFIAPI
 327 ArmInvalidateTlb (
 328   VOID
 329   );
 330
 331 VOID
 332 EFIAPI
 333 ArmUpdateTranslationTableEntry (
 334   IN  VOID     *TranslationTableEntry,
 335   IN  VOID     *Mva
 336   );
 337
 338 VOID
 339 EFIAPI
 340 ArmSetDomainAccessControl (
 341   IN  UINT32  Domain
 342   );
 343
 344 VOID
 345 EFIAPI
 346 ArmSetTTBR0 (
 347   IN  VOID  *TranslationTableBase
 348   );
 349
 350 VOID
 351 EFIAPI
 352 ArmSetTTBCR (
 353   IN  UINT32 Bits
 354   );
 355
 356 VOID *
 357 EFIAPI
 358 ArmGetTTBR0BaseAddress (
 359   VOID
 360   );
 361
 362 BOOLEAN
 363 EFIAPI
 364 ArmMmuEnabled (
 365   VOID
 366   );
 367
 368 VOID
 369 EFIAPI
 370 ArmEnableBranchPrediction (
 371   VOID
 372   );
 373
 374 VOID
 375 EFIAPI
 376 ArmDisableBranchPrediction (
 377   VOID
 378   );
 379
 380 VOID
 381 EFIAPI
 382 ArmSetLowVectors (
 383   VOID
 384   );
 385
 386 VOID
 387 EFIAPI
 388 ArmSetHighVectors (
 389   VOID
 390   );
 391
 392 VOID
 393 EFIAPI
 394 ArmDataMemoryBarrier (
 395   VOID
 396   );
 397
 398 VOID
 399 EFIAPI
 400 ArmDataSynchronizationBarrier (
 401   VOID
 402   );
 403
 404 VOID
 405 EFIAPI
 406 ArmInstructionSynchronizationBarrier (
 407   VOID
 408   );
 409
 410 VOID
 411 EFIAPI
 412 ArmWriteVBar (
 413   IN  UINTN   VectorBase
 414   );
 415
 416 UINTN
 417 EFIAPI
 418 ArmReadVBar (
 419   VOID
 420   );
 421
 422 VOID
 423 EFIAPI
 424 ArmWriteAuxCr (
 425   IN  UINT32    Bit
 426   );
 427
 428 UINT32
 429 EFIAPI
 430 ArmReadAuxCr (
 431   VOID
 432   );
 433
 434 VOID
 435 EFIAPI
 436 ArmSetAuxCrBit (
 437   IN  UINT32    Bits
 438   );
 439
 440 VOID
 441 EFIAPI
 442 ArmUnsetAuxCrBit (
 443   IN  UINT32    Bits
 444   );
 445
 446 VOID
 447 EFIAPI
 448 ArmCallSEV (
 449   VOID
 450   );
 451
 452 VOID
 453 EFIAPI
 454 ArmCallWFE (
 455   VOID
 456   );
 457
 458 VOID
 459 EFIAPI
 460 ArmCallWFI (
 461
 462   VOID
 463   );
 464
 465 UINTN
 466 EFIAPI
 467 ArmReadMpidr (
 468   VOID
 469   );
 470
 471 UINTN
 472 EFIAPI
 473 ArmReadMidr (
 474   VOID
 475   );
 476
 477 UINT32
 478 EFIAPI
 479 ArmReadCpacr (
 480   VOID
 481   );
 482
 483 VOID
 484 EFIAPI
 485 ArmWriteCpacr (
 486   IN  UINT32   Access
 487   );
 488
 489 VOID
 490 EFIAPI
 491 ArmEnableVFP (
 492   VOID
 493   );
 494
 495 /**
 496   Get the Secure Configuration Register value
 497
 498   @return   Value read from the Secure Configuration Register
 499
 500 **/
 501 UINT32
 502 EFIAPI
 503 ArmReadScr (
 504   VOID
 505   );
 506
 507 /**
 508   Set the Secure Configuration Register
 509
 510   @param Value   Value to write to the Secure Configuration Register
 511
 512 **/
 513 VOID
 514 EFIAPI
 515 ArmWriteScr (
 516   IN  UINT32   Value
 517   );
 518
 519 UINT32
 520 EFIAPI
 521 ArmReadMVBar (
 522   VOID
 523   );
 524
 525 VOID
 526 EFIAPI
 527 ArmWriteMVBar (
 528   IN  UINT32   VectorMonitorBase
 529   );
 530
 531 UINT32
 532 EFIAPI
 533 ArmReadSctlr (
 534   VOID
 535   );
 536
 537 VOID
 538 EFIAPI
 539 ArmWriteSctlr (
 540   IN  UINT32   Value
 541   );
 542
 543 UINTN
 544 EFIAPI
 545 ArmReadHVBar (
 546   VOID
 547   );
 548
 549 VOID
 550 EFIAPI
 551 ArmWriteHVBar (
 552   IN  UINTN   HypModeVectorBase
 553   );
 554
 555
 556 //
 557 // Helper functions for accessing CPU ACTLR
 558 //
 559
 560 UINTN
 561 EFIAPI
 562 ArmReadCpuActlr (
 563   VOID
 564   );
 565
 566 VOID
 567 EFIAPI
 568 ArmWriteCpuActlr (
 569   IN  UINTN Val
 570   );
 571
 572 VOID
 573 EFIAPI
 574 ArmSetCpuActlrBit (
 575   IN  UINTN    Bits
 576   );
 577
 578 VOID
 579 EFIAPI
 580 ArmUnsetCpuActlrBit (
 581   IN  UINTN    Bits
 582   );
 583
 584 //
 585 // Accessors for the architected generic timer registers
 586 //
 587
 588 #define ARM_ARCH_TIMER_ENABLE           (1 << 0)
 589 #define ARM_ARCH_TIMER_IMASK            (1 << 1)
 590 #define ARM_ARCH_TIMER_ISTATUS          (1 << 2)
 591
 592 UINTN
 593 EFIAPI
 594 ArmReadCntFrq (
 595   VOID
 596   );
 597
 598 VOID
 599 EFIAPI
 600 ArmWriteCntFrq (
 601   UINTN   FreqInHz
 602   );
 603
 604 UINT64
 605 EFIAPI
 606 ArmReadCntPct (
 607   VOID
 608   );
 609
 610 UINTN
 611 EFIAPI
 612 ArmReadCntkCtl (
 613   VOID
 614   );
 615
 616 VOID
 617 EFIAPI
 618 ArmWriteCntkCtl (
 619   UINTN   Val
 620   );
 621
 622 UINTN
 623 EFIAPI
 624 ArmReadCntpTval (
 625   VOID
 626   );
 627
 628 VOID
 629 EFIAPI
 630 ArmWriteCntpTval (
 631   UINTN   Val
 632   );
 633
 634 UINTN
 635 EFIAPI
 636 ArmReadCntpCtl (
 637   VOID
 638   );
 639
 640 VOID
 641 EFIAPI
 642 ArmWriteCntpCtl (
 643   UINTN   Val
 644   );
 645
 646 UINTN
 647 EFIAPI
 648 ArmReadCntvTval (
 649   VOID
 650   );
 651
 652 VOID
 653 EFIAPI
 654 ArmWriteCntvTval (
 655   UINTN   Val
 656   );
 657
 658 UINTN
 659 EFIAPI
 660 ArmReadCntvCtl (
 661   VOID
 662   );
 663
 664 VOID
 665 EFIAPI
 666 ArmWriteCntvCtl (
 667   UINTN   Val
 668   );
 669
 670 UINT64
 671 EFIAPI
 672 ArmReadCntvCt (
 673   VOID
 674   );
 675
 676 UINT64
 677 EFIAPI
 678 ArmReadCntpCval (
 679   VOID
 680   );
 681
 682 VOID
 683 EFIAPI
 684 ArmWriteCntpCval (
 685   UINT64   Val
 686   );
 687
 688 UINT64
 689 EFIAPI
 690 ArmReadCntvCval (
 691   VOID
 692   );
 693
 694 VOID
 695 EFIAPI
 696 ArmWriteCntvCval (
 697   UINT64   Val
 698   );
 699
 700 UINT64
 701 EFIAPI
 702 ArmReadCntvOff (
 703   VOID
 704   );
 705
 706 VOID
 707 EFIAPI
 708 ArmWriteCntvOff (
 709   UINT64   Val
 710   );
 711
 712 UINTN
 713 EFIAPI
 714 ArmGetPhysicalAddressBits (
 715   VOID
 716   );
 717
 718 #endif // __ARM_LIB__