ArmPkg/Include/Library/ArmLib.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef __ARM_LIB__
  16 #define __ARM_LIB__
  17
  18 typedef enum {
  19   ARM_CACHE_TYPE_WRITE_BACK,
  20   ARM_CACHE_TYPE_UNKNOWN
  21 } ARM_CACHE_TYPE;
  22
  23 typedef enum {
  24   ARM_CACHE_ARCHITECTURE_UNIFIED,
  25   ARM_CACHE_ARCHITECTURE_SEPARATE,
  26   ARM_CACHE_ARCHITECTURE_UNKNOWN
  27 } ARM_CACHE_ARCHITECTURE;
  28
  29 typedef struct {
  30   ARM_CACHE_TYPE          Type;
  31   ARM_CACHE_ARCHITECTURE  Architecture;
  32   BOOLEAN                 DataCachePresent;
  33   UINTN                   DataCacheSize;
  34   UINTN                   DataCacheAssociativity;
  35   UINTN                   DataCacheLineLength;
  36   BOOLEAN                 InstructionCachePresent;
  37   UINTN                   InstructionCacheSize;
  38   UINTN                   InstructionCacheAssociativity;
  39   UINTN                   InstructionCacheLineLength;
  40 } ARM_CACHE_INFO;
  41
  42 typedef enum {
  43   ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,
  44   ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED,
  45   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
  46   ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK,
  47   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
  48   ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH,
  49   ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
  50   ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE
  51 } ARM_MEMORY_REGION_ATTRIBUTES;
  52
  53 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
  54
  55 typedef struct {
  56   UINT32                        PhysicalBase;
  57   UINT32                        VirtualBase;
  58   UINT32                        Length;
  59   ARM_MEMORY_REGION_ATTRIBUTES  Attributes;
  60 } ARM_MEMORY_REGION_DESCRIPTOR;
  61
  62 typedef VOID (*CACHE_OPERATION)(VOID);
  63 typedef VOID (*LINE_OPERATION)(UINTN);
  64
  65 typedef enum {
  66   ARM_PROCESSOR_MODE_USER       = 0x10,
  67   ARM_PROCESSOR_MODE_FIQ        = 0x11,
  68   ARM_PROCESSOR_MODE_IRQ        = 0x12,
  69   ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
  70   ARM_PROCESSOR_MODE_ABORT      = 0x17,
  71   ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,
  72   ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,
  73   ARM_PROCESSOR_MODE_MASK       = 0x1F
  74 } ARM_PROCESSOR_MODE;
  75
  76 #define IS_PRIMARY_CORE(MpId) (((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore))
  77 #define GET_CORE_ID(MpId)     ((MpId) & 0x3)
  78 #define GET_CLUSTER_ID(MpId)  (((MpId) >> 6) & 0x3C)
  79 // Get the position of the core for the Stack Offset (4 Core per Cluster)
  80 //   Position = (ClusterId * 4) + CoreId
  81 #define GET_CORE_POS(MpId)    ((((MpId) >> 6) & 0x3C) + ((MpId) & 0x3))
  82 #define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & 0x3)
  83
  84 ARM_CACHE_TYPE
  85 EFIAPI
  86 ArmCacheType (
  87   VOID
  88   );
  89
  90 ARM_CACHE_ARCHITECTURE
  91 EFIAPI
  92 ArmCacheArchitecture (
  93   VOID
  94   );
  95
  96 VOID
  97 EFIAPI
  98 ArmCacheInformation (
  99   OUT ARM_CACHE_INFO  *CacheInfo
 100   );
 101
 102 BOOLEAN
 103 EFIAPI
 104 ArmDataCachePresent (
 105   VOID
 106   );
 107
 108 UINTN
 109 EFIAPI
 110 ArmDataCacheSize (
 111   VOID
 112   );
 113
 114 UINTN
 115 EFIAPI
 116 ArmDataCacheAssociativity (
 117   VOID
 118   );
 119
 120 UINTN
 121 EFIAPI
 122 ArmDataCacheLineLength (
 123   VOID
 124   );
 125
 126 BOOLEAN
 127 EFIAPI
 128 ArmInstructionCachePresent (
 129   VOID
 130   );
 131
 132 UINTN
 133 EFIAPI
 134 ArmInstructionCacheSize (
 135   VOID
 136   );
 137
 138 UINTN
 139 EFIAPI
 140 ArmInstructionCacheAssociativity (
 141   VOID
 142   );
 143
 144 UINTN
 145 EFIAPI
 146 ArmInstructionCacheLineLength (
 147   VOID
 148   );
 149
 150 UINT32
 151 EFIAPI
 152 Cp15IdCode (
 153   VOID
 154   );
 155
 156 UINT32
 157 EFIAPI
 158 Cp15CacheInfo (
 159   VOID
 160   );
 161
 162 BOOLEAN
 163 EFIAPI
 164 ArmIsMPCore (
 165   VOID
 166   );
 167
 168 VOID
 169 EFIAPI
 170 ArmInvalidateDataCache (
 171   VOID
 172   );
 173
 174
 175 VOID
 176 EFIAPI
 177 ArmCleanInvalidateDataCache (
 178   VOID
 179   );
 180
 181 VOID
 182 EFIAPI
 183 ArmCleanDataCache (
 184   VOID
 185   );
 186
 187 VOID
 188 EFIAPI
 189 ArmInvalidateInstructionCache (
 190   VOID
 191   );
 192
 193 VOID
 194 EFIAPI
 195 ArmInvalidateDataCacheEntryByMVA (
 196   IN  UINTN   Address
 197   );
 198
 199 VOID
 200 EFIAPI
 201 ArmCleanDataCacheEntryByMVA (
 202   IN  UINTN   Address
 203   );
 204
 205 VOID
 206 EFIAPI
 207 ArmCleanInvalidateDataCacheEntryByMVA (
 208   IN  UINTN   Address
 209   );
 210
 211 VOID
 212 EFIAPI
 213 ArmEnableDataCache (
 214   VOID
 215   );
 216
 217 VOID
 218 EFIAPI
 219 ArmDisableDataCache (
 220   VOID
 221   );
 222
 223 VOID
 224 EFIAPI
 225 ArmEnableInstructionCache (
 226   VOID
 227   );
 228
 229 VOID
 230 EFIAPI
 231 ArmDisableInstructionCache (
 232   VOID
 233   );
 234
 235 VOID
 236 EFIAPI
 237 ArmEnableMmu (
 238   VOID
 239   );
 240
 241 VOID
 242 EFIAPI
 243 ArmDisableMmu (
 244   VOID
 245   );
 246
 247 VOID
 248 EFIAPI
 249 ArmDisableCachesAndMmu (
 250   VOID
 251   );
 252
 253 VOID
 254 EFIAPI
 255 ArmEnableInterrupts (
 256   VOID
 257   );
 258
 259 UINTN
 260 EFIAPI
 261 ArmDisableInterrupts (
 262   VOID
 263   );
 264
 265 BOOLEAN
 266 EFIAPI
 267 ArmGetInterruptState (
 268   VOID
 269   );
 270
 271 VOID
 272 EFIAPI
 273 ArmEnableFiq (
 274   VOID
 275   );
 276
 277 UINTN
 278 EFIAPI
 279 ArmDisableFiq (
 280   VOID
 281   );
 282
 283 BOOLEAN
 284 EFIAPI
 285 ArmGetFiqState (
 286   VOID
 287   );
 288
 289 VOID
 290 EFIAPI
 291 ArmInvalidateTlb (
 292   VOID
 293   );
 294
 295 VOID
 296 EFIAPI
 297 ArmUpdateTranslationTableEntry (
 298   IN  VOID     *TranslationTableEntry,
 299   IN  VOID     *Mva
 300   );
 301
 302 VOID
 303 EFIAPI
 304 ArmSetDomainAccessControl (
 305   IN  UINT32  Domain
 306   );
 307
 308 VOID
 309 EFIAPI
 310 ArmSetTTBR0 (
 311   IN  VOID  *TranslationTableBase
 312   );
 313
 314 VOID *
 315 EFIAPI
 316 ArmGetTTBR0BaseAddress (
 317   VOID
 318   );
 319
 320 VOID
 321 EFIAPI
 322 ArmConfigureMmu (
 323   IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,
 324   OUT VOID                          **TranslationTableBase OPTIONAL,
 325   OUT UINTN                         *TranslationTableSize  OPTIONAL
 326   );
 327
 328 BOOLEAN
 329 EFIAPI
 330 ArmMmuEnabled (
 331   VOID
 332   );
 333
 334 VOID
 335 EFIAPI
 336 ArmSwitchProcessorMode (
 337   IN ARM_PROCESSOR_MODE Mode
 338   );
 339
 340 ARM_PROCESSOR_MODE
 341 EFIAPI
 342 ArmProcessorMode (
 343   VOID
 344   );
 345
 346 VOID
 347 EFIAPI
 348 ArmEnableBranchPrediction (
 349   VOID
 350   );
 351
 352 VOID
 353 EFIAPI
 354 ArmDisableBranchPrediction (
 355   VOID
 356   );
 357
 358 VOID
 359 EFIAPI
 360 ArmSetLowVectors (
 361   VOID
 362   );
 363
 364 VOID
 365 EFIAPI
 366 ArmSetHighVectors (
 367   VOID
 368   );
 369
 370 VOID
 371 EFIAPI
 372 ArmDataMemoryBarrier (
 373   VOID
 374   );
 375
 376 VOID
 377 EFIAPI
 378 ArmDataSyncronizationBarrier (
 379   VOID
 380   );
 381
 382 VOID
 383 EFIAPI
 384 ArmInstructionSynchronizationBarrier (
 385   VOID
 386   );
 387
 388
 389 #endif // __ARM_LIB__