ArmPkg/Include/Library/ArmLib.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
   5   Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>
   6
   7   SPDX-License-Identifier: BSD-2-Clause-Patent
   8
   9 **/
  10
  11 #ifndef __ARM_LIB__
  12 #define __ARM_LIB__
  13
  14 #include <Uefi/UefiBaseType.h>
  15
  16 #ifdef MDE_CPU_ARM
  17   #include <Chipset/ArmV7.h>
  18 #elif defined(MDE_CPU_AARCH64)
  19   #include <Chipset/AArch64.h>
  20 #else
  21  #error "Unknown chipset."
  22 #endif
  23
  24 #define EFI_MEMORY_CACHETYPE_MASK   (EFI_MEMORY_UC | EFI_MEMORY_WC | \
  25                                      EFI_MEMORY_WT | EFI_MEMORY_WB | \
  26                                      EFI_MEMORY_UCE)
  27
  28 /**
  29  * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
  30  *
  31  * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
  32  * be used in Secure World to distinguished Secure to Non-Secure memory.
  33  */
  34 typedef enum {
  35   ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,
  36   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,
  37   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
  38   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,
  39
  40   // On some platforms, memory mapped flash region is designed as not supporting
  41   // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special
  42   // need.
  43   // Do NOT use below two attributes if you are not sure.
  44   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,
  45   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,
  46
  47   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
  48   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,
  49   ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
  50   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
  51 } ARM_MEMORY_REGION_ATTRIBUTES;
  52
  53 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
  54
  55 typedef struct {
  56   EFI_PHYSICAL_ADDRESS          PhysicalBase;
  57   EFI_VIRTUAL_ADDRESS           VirtualBase;
  58   UINT64                        Length;
  59   ARM_MEMORY_REGION_ATTRIBUTES  Attributes;
  60 } ARM_MEMORY_REGION_DESCRIPTOR;
  61
  62 typedef VOID (*CACHE_OPERATION)(VOID);
  63 typedef VOID (*LINE_OPERATION)(UINTN);
  64
  65 //
  66 // ARM Processor Mode
  67 //
  68 typedef enum {
  69   ARM_PROCESSOR_MODE_USER       = 0x10,
  70   ARM_PROCESSOR_MODE_FIQ        = 0x11,
  71   ARM_PROCESSOR_MODE_IRQ        = 0x12,
  72   ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
  73   ARM_PROCESSOR_MODE_ABORT      = 0x17,
  74   ARM_PROCESSOR_MODE_HYP        = 0x1A,
  75   ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,
  76   ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,
  77   ARM_PROCESSOR_MODE_MASK       = 0x1F
  78 } ARM_PROCESSOR_MODE;
  79
  80 //
  81 // ARM Cpu IDs
  82 //
  83 #define ARM_CPU_IMPLEMENTER_MASK          (0xFFU << 24)
  84 #define ARM_CPU_IMPLEMENTER_ARMLTD        (0x41U << 24)
  85 #define ARM_CPU_IMPLEMENTER_DEC           (0x44U << 24)
  86 #define ARM_CPU_IMPLEMENTER_MOT           (0x4DU << 24)
  87 #define ARM_CPU_IMPLEMENTER_QUALCOMM      (0x51U << 24)
  88 #define ARM_CPU_IMPLEMENTER_MARVELL       (0x56U << 24)
  89
  90 #define ARM_CPU_PRIMARY_PART_MASK         (0xFFF << 4)
  91 #define ARM_CPU_PRIMARY_PART_CORTEXA5     (0xC05 << 4)
  92 #define ARM_CPU_PRIMARY_PART_CORTEXA7     (0xC07 << 4)
  93 #define ARM_CPU_PRIMARY_PART_CORTEXA8     (0xC08 << 4)
  94 #define ARM_CPU_PRIMARY_PART_CORTEXA9     (0xC09 << 4)
  95 #define ARM_CPU_PRIMARY_PART_CORTEXA15    (0xC0F << 4)
  96
  97 //
  98 // ARM MP Core IDs
  99 //
 100 #define ARM_CORE_AFF0         0xFF
 101 #define ARM_CORE_AFF1         (0xFF << 8)
 102 #define ARM_CORE_AFF2         (0xFF << 16)
 103 #define ARM_CORE_AFF3         (0xFFULL << 32)
 104
 105 #define ARM_CORE_MASK         ARM_CORE_AFF0
 106 #define ARM_CLUSTER_MASK      ARM_CORE_AFF1
 107 #define GET_CORE_ID(MpId)     ((MpId) & ARM_CORE_MASK)
 108 #define GET_CLUSTER_ID(MpId)  (((MpId) & ARM_CLUSTER_MASK) >> 8)
 109 #define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))
 110 #define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
 111
 112 UINTN
 113 EFIAPI
 114 ArmDataCacheLineLength (
 115   VOID
 116   );
 117
 118 UINTN
 119 EFIAPI
 120 ArmInstructionCacheLineLength (
 121   VOID
 122   );
 123
 124 UINTN
 125 EFIAPI
 126 ArmCacheWritebackGranule (
 127   VOID
 128   );
 129
 130 UINTN
 131 EFIAPI
 132 ArmIsArchTimerImplemented (
 133   VOID
 134   );
 135
 136 UINTN
 137 EFIAPI
 138 ArmReadIdPfr0 (
 139   VOID
 140   );
 141
 142 UINTN
 143 EFIAPI
 144 ArmReadIdPfr1 (
 145   VOID
 146   );
 147
 148 UINTN
 149 EFIAPI
 150 ArmCacheInfo (
 151   VOID
 152   );
 153
 154 BOOLEAN
 155 EFIAPI
 156 ArmIsMpCore (
 157   VOID
 158   );
 159
 160 VOID
 161 EFIAPI
 162 ArmInvalidateDataCache (
 163   VOID
 164   );
 165
 166
 167 VOID
 168 EFIAPI
 169 ArmCleanInvalidateDataCache (
 170   VOID
 171   );
 172
 173 VOID
 174 EFIAPI
 175 ArmCleanDataCache (
 176   VOID
 177   );
 178
 179 VOID
 180 EFIAPI
 181 ArmInvalidateInstructionCache (
 182   VOID
 183   );
 184
 185 VOID
 186 EFIAPI
 187 ArmInvalidateDataCacheEntryByMVA (
 188   IN  UINTN   Address
 189   );
 190
 191 VOID
 192 EFIAPI
 193 ArmCleanDataCacheEntryToPoUByMVA (
 194   IN  UINTN   Address
 195   );
 196
 197 VOID
 198 EFIAPI
 199 ArmInvalidateInstructionCacheEntryToPoUByMVA (
 200   IN  UINTN   Address
 201   );
 202
 203 VOID
 204 EFIAPI
 205 ArmCleanDataCacheEntryByMVA (
 206 IN  UINTN   Address
 207 );
 208
 209 VOID
 210 EFIAPI
 211 ArmCleanInvalidateDataCacheEntryByMVA (
 212   IN  UINTN   Address
 213   );
 214
 215 VOID
 216 EFIAPI
 217 ArmEnableDataCache (
 218   VOID
 219   );
 220
 221 VOID
 222 EFIAPI
 223 ArmDisableDataCache (
 224   VOID
 225   );
 226
 227 VOID
 228 EFIAPI
 229 ArmEnableInstructionCache (
 230   VOID
 231   );
 232
 233 VOID
 234 EFIAPI
 235 ArmDisableInstructionCache (
 236   VOID
 237   );
 238
 239 VOID
 240 EFIAPI
 241 ArmEnableMmu (
 242   VOID
 243   );
 244
 245 VOID
 246 EFIAPI
 247 ArmDisableMmu (
 248   VOID
 249   );
 250
 251 VOID
 252 EFIAPI
 253 ArmEnableCachesAndMmu (
 254   VOID
 255   );
 256
 257 VOID
 258 EFIAPI
 259 ArmDisableCachesAndMmu (
 260   VOID
 261   );
 262
 263 VOID
 264 EFIAPI
 265 ArmEnableInterrupts (
 266   VOID
 267   );
 268
 269 UINTN
 270 EFIAPI
 271 ArmDisableInterrupts (
 272   VOID
 273   );
 274
 275 BOOLEAN
 276 EFIAPI
 277 ArmGetInterruptState (
 278   VOID
 279   );
 280
 281 VOID
 282 EFIAPI
 283 ArmEnableAsynchronousAbort (
 284   VOID
 285   );
 286
 287 UINTN
 288 EFIAPI
 289 ArmDisableAsynchronousAbort (
 290   VOID
 291   );
 292
 293 VOID
 294 EFIAPI
 295 ArmEnableIrq (
 296   VOID
 297   );
 298
 299 UINTN
 300 EFIAPI
 301 ArmDisableIrq (
 302   VOID
 303   );
 304
 305 VOID
 306 EFIAPI
 307 ArmEnableFiq (
 308   VOID
 309   );
 310
 311 UINTN
 312 EFIAPI
 313 ArmDisableFiq (
 314   VOID
 315   );
 316
 317 BOOLEAN
 318 EFIAPI
 319 ArmGetFiqState (
 320   VOID
 321   );
 322
 323 /**
 324  * Invalidate Data and Instruction TLBs
 325  */
 326 VOID
 327 EFIAPI
 328 ArmInvalidateTlb (
 329   VOID
 330   );
 331
 332 VOID
 333 EFIAPI
 334 ArmUpdateTranslationTableEntry (
 335   IN  VOID     *TranslationTableEntry,
 336   IN  VOID     *Mva
 337   );
 338
 339 VOID
 340 EFIAPI
 341 ArmSetDomainAccessControl (
 342   IN  UINT32  Domain
 343   );
 344
 345 VOID
 346 EFIAPI
 347 ArmSetTTBR0 (
 348   IN  VOID  *TranslationTableBase
 349   );
 350
 351 VOID
 352 EFIAPI
 353 ArmSetTTBCR (
 354   IN  UINT32 Bits
 355   );
 356
 357 VOID *
 358 EFIAPI
 359 ArmGetTTBR0BaseAddress (
 360   VOID
 361   );
 362
 363 BOOLEAN
 364 EFIAPI
 365 ArmMmuEnabled (
 366   VOID
 367   );
 368
 369 VOID
 370 EFIAPI
 371 ArmEnableBranchPrediction (
 372   VOID
 373   );
 374
 375 VOID
 376 EFIAPI
 377 ArmDisableBranchPrediction (
 378   VOID
 379   );
 380
 381 VOID
 382 EFIAPI
 383 ArmSetLowVectors (
 384   VOID
 385   );
 386
 387 VOID
 388 EFIAPI
 389 ArmSetHighVectors (
 390   VOID
 391   );
 392
 393 VOID
 394 EFIAPI
 395 ArmDataMemoryBarrier (
 396   VOID
 397   );
 398
 399 VOID
 400 EFIAPI
 401 ArmDataSynchronizationBarrier (
 402   VOID
 403   );
 404
 405 VOID
 406 EFIAPI
 407 ArmInstructionSynchronizationBarrier (
 408   VOID
 409   );
 410
 411 VOID
 412 EFIAPI
 413 ArmWriteVBar (
 414   IN  UINTN   VectorBase
 415   );
 416
 417 UINTN
 418 EFIAPI
 419 ArmReadVBar (
 420   VOID
 421   );
 422
 423 VOID
 424 EFIAPI
 425 ArmWriteAuxCr (
 426   IN  UINT32    Bit
 427   );
 428
 429 UINT32
 430 EFIAPI
 431 ArmReadAuxCr (
 432   VOID
 433   );
 434
 435 VOID
 436 EFIAPI
 437 ArmSetAuxCrBit (
 438   IN  UINT32    Bits
 439   );
 440
 441 VOID
 442 EFIAPI
 443 ArmUnsetAuxCrBit (
 444   IN  UINT32    Bits
 445   );
 446
 447 VOID
 448 EFIAPI
 449 ArmCallSEV (
 450   VOID
 451   );
 452
 453 VOID
 454 EFIAPI
 455 ArmCallWFE (
 456   VOID
 457   );
 458
 459 VOID
 460 EFIAPI
 461 ArmCallWFI (
 462
 463   VOID
 464   );
 465
 466 UINTN
 467 EFIAPI
 468 ArmReadMpidr (
 469   VOID
 470   );
 471
 472 UINTN
 473 EFIAPI
 474 ArmReadMidr (
 475   VOID
 476   );
 477
 478 UINT32
 479 EFIAPI
 480 ArmReadCpacr (
 481   VOID
 482   );
 483
 484 VOID
 485 EFIAPI
 486 ArmWriteCpacr (
 487   IN  UINT32   Access
 488   );
 489
 490 VOID
 491 EFIAPI
 492 ArmEnableVFP (
 493   VOID
 494   );
 495
 496 /**
 497   Get the Secure Configuration Register value
 498
 499   @return   Value read from the Secure Configuration Register
 500
 501 **/
 502 UINT32
 503 EFIAPI
 504 ArmReadScr (
 505   VOID
 506   );
 507
 508 /**
 509   Set the Secure Configuration Register
 510
 511   @param Value   Value to write to the Secure Configuration Register
 512
 513 **/
 514 VOID
 515 EFIAPI
 516 ArmWriteScr (
 517   IN  UINT32   Value
 518   );
 519
 520 UINT32
 521 EFIAPI
 522 ArmReadMVBar (
 523   VOID
 524   );
 525
 526 VOID
 527 EFIAPI
 528 ArmWriteMVBar (
 529   IN  UINT32   VectorMonitorBase
 530   );
 531
 532 UINT32
 533 EFIAPI
 534 ArmReadSctlr (
 535   VOID
 536   );
 537
 538 VOID
 539 EFIAPI
 540 ArmWriteSctlr (
 541   IN  UINT32   Value
 542   );
 543
 544 UINTN
 545 EFIAPI
 546 ArmReadHVBar (
 547   VOID
 548   );
 549
 550 VOID
 551 EFIAPI
 552 ArmWriteHVBar (
 553   IN  UINTN   HypModeVectorBase
 554   );
 555
 556
 557 //
 558 // Helper functions for accessing CPU ACTLR
 559 //
 560
 561 UINTN
 562 EFIAPI
 563 ArmReadCpuActlr (
 564   VOID
 565   );
 566
 567 VOID
 568 EFIAPI
 569 ArmWriteCpuActlr (
 570   IN  UINTN Val
 571   );
 572
 573 VOID
 574 EFIAPI
 575 ArmSetCpuActlrBit (
 576   IN  UINTN    Bits
 577   );
 578
 579 VOID
 580 EFIAPI
 581 ArmUnsetCpuActlrBit (
 582   IN  UINTN    Bits
 583   );
 584
 585 //
 586 // Accessors for the architected generic timer registers
 587 //
 588
 589 #define ARM_ARCH_TIMER_ENABLE           (1 << 0)
 590 #define ARM_ARCH_TIMER_IMASK            (1 << 1)
 591 #define ARM_ARCH_TIMER_ISTATUS          (1 << 2)
 592
 593 UINTN
 594 EFIAPI
 595 ArmReadCntFrq (
 596   VOID
 597   );
 598
 599 VOID
 600 EFIAPI
 601 ArmWriteCntFrq (
 602   UINTN   FreqInHz
 603   );
 604
 605 UINT64
 606 EFIAPI
 607 ArmReadCntPct (
 608   VOID
 609   );
 610
 611 UINTN
 612 EFIAPI
 613 ArmReadCntkCtl (
 614   VOID
 615   );
 616
 617 VOID
 618 EFIAPI
 619 ArmWriteCntkCtl (
 620   UINTN   Val
 621   );
 622
 623 UINTN
 624 EFIAPI
 625 ArmReadCntpTval (
 626   VOID
 627   );
 628
 629 VOID
 630 EFIAPI
 631 ArmWriteCntpTval (
 632   UINTN   Val
 633   );
 634
 635 UINTN
 636 EFIAPI
 637 ArmReadCntpCtl (
 638   VOID
 639   );
 640
 641 VOID
 642 EFIAPI
 643 ArmWriteCntpCtl (
 644   UINTN   Val
 645   );
 646
 647 UINTN
 648 EFIAPI
 649 ArmReadCntvTval (
 650   VOID
 651   );
 652
 653 VOID
 654 EFIAPI
 655 ArmWriteCntvTval (
 656   UINTN   Val
 657   );
 658
 659 UINTN
 660 EFIAPI
 661 ArmReadCntvCtl (
 662   VOID
 663   );
 664
 665 VOID
 666 EFIAPI
 667 ArmWriteCntvCtl (
 668   UINTN   Val
 669   );
 670
 671 UINT64
 672 EFIAPI
 673 ArmReadCntvCt (
 674   VOID
 675   );
 676
 677 UINT64
 678 EFIAPI
 679 ArmReadCntpCval (
 680   VOID
 681   );
 682
 683 VOID
 684 EFIAPI
 685 ArmWriteCntpCval (
 686   UINT64   Val
 687   );
 688
 689 UINT64
 690 EFIAPI
 691 ArmReadCntvCval (
 692   VOID
 693   );
 694
 695 VOID
 696 EFIAPI
 697 ArmWriteCntvCval (
 698   UINT64   Val
 699   );
 700
 701 UINT64
 702 EFIAPI
 703 ArmReadCntvOff (
 704   VOID
 705   );
 706
 707 VOID
 708 EFIAPI
 709 ArmWriteCntvOff (
 710   UINT64   Val
 711   );
 712
 713 UINTN
 714 EFIAPI
 715 ArmGetPhysicalAddressBits (
 716   VOID
 717   );
 718
 719
 720 ///
 721 ///  ID Register Helper functions
 722 ///
 723
 724 /**
 725   Check whether the CPU supports the GIC system register interface (any version)
 726
 727   @return   Whether GIC System Register Interface is supported
 728
 729 **/
 730 BOOLEAN
 731 EFIAPI
 732 ArmHasGicSystemRegisters (
 733   VOID
 734   );
 735
 736 #ifdef MDE_CPU_ARM
 737 ///
 738 /// AArch32-only ID Register Helper functions
 739 ///
 740 /**
 741   Check whether the CPU supports the Security extensions
 742
 743   @return   Whether the Security extensions are implemented
 744
 745 **/
 746 BOOLEAN
 747 EFIAPI
 748 ArmHasSecurityExtensions (
 749   VOID
 750   );
 751 #endif // MDE_CPU_ARM
 752
 753 #endif // __ARM_LIB__