d68b334e2aab32c7bfc96b59442e4672a7c02011
[mirror_edk2.git] / ArmPkg / Include / Library / ArmLib.h
1 /** @file
2
3 Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
4
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #ifndef __ARM_LIB__
16 #define __ARM_LIB__
17
18 typedef enum {
19 ARM_CACHE_TYPE_WRITE_BACK,
20 ARM_CACHE_TYPE_UNKNOWN
21 } ARM_CACHE_TYPE;
22
23 typedef enum {
24 ARM_CACHE_ARCHITECTURE_UNIFIED,
25 ARM_CACHE_ARCHITECTURE_SEPARATE,
26 ARM_CACHE_ARCHITECTURE_UNKNOWN
27 } ARM_CACHE_ARCHITECTURE;
28
29 typedef struct {
30 ARM_CACHE_TYPE Type;
31 ARM_CACHE_ARCHITECTURE Architecture;
32 BOOLEAN DataCachePresent;
33 UINTN DataCacheSize;
34 UINTN DataCacheAssociativity;
35 UINTN DataCacheLineLength;
36 BOOLEAN InstructionCachePresent;
37 UINTN InstructionCacheSize;
38 UINTN InstructionCacheAssociativity;
39 UINTN InstructionCacheLineLength;
40 } ARM_CACHE_INFO;
41
42 typedef enum {
43 ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED,
44 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
45 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
46 ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
47 } ARM_MEMORY_REGION_ATTRIBUTES;
48
49 typedef struct {
50 UINT32 PhysicalBase;
51 UINT32 VirtualBase;
52 UINT32 Length;
53 ARM_MEMORY_REGION_ATTRIBUTES Attributes;
54 } ARM_MEMORY_REGION_DESCRIPTOR;
55
56 typedef VOID (*CACHE_OPERATION)(VOID);
57 typedef VOID (*LINE_OPERATION)(UINTN);
58
59 typedef enum {
60 ARM_PROCESSOR_MODE_USER = 0x10,
61 ARM_PROCESSOR_MODE_FIQ = 0x11,
62 ARM_PROCESSOR_MODE_IRQ = 0x12,
63 ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
64 ARM_PROCESSOR_MODE_ABORT = 0x17,
65 ARM_PROCESSOR_MODE_UNDEFINED = 0x1B,
66 ARM_PROCESSOR_MODE_SYSTEM = 0x1F,
67 ARM_PROCESSOR_MODE_MASK = 0x1F
68 } ARM_PROCESSOR_MODE;
69
70 ARM_CACHE_TYPE
71 EFIAPI
72 ArmCacheType (
73 VOID
74 );
75
76 ARM_CACHE_ARCHITECTURE
77 EFIAPI
78 ArmCacheArchitecture (
79 VOID
80 );
81
82 VOID
83 EFIAPI
84 ArmCacheInformation (
85 OUT ARM_CACHE_INFO *CacheInfo
86 );
87
88 BOOLEAN
89 EFIAPI
90 ArmDataCachePresent (
91 VOID
92 );
93
94 UINTN
95 EFIAPI
96 ArmDataCacheSize (
97 VOID
98 );
99
100 UINTN
101 EFIAPI
102 ArmDataCacheAssociativity (
103 VOID
104 );
105
106 UINTN
107 EFIAPI
108 ArmDataCacheLineLength (
109 VOID
110 );
111
112 BOOLEAN
113 EFIAPI
114 ArmInstructionCachePresent (
115 VOID
116 );
117
118 UINTN
119 EFIAPI
120 ArmInstructionCacheSize (
121 VOID
122 );
123
124 UINTN
125 EFIAPI
126 ArmInstructionCacheAssociativity (
127 VOID
128 );
129
130 UINTN
131 EFIAPI
132 ArmInstructionCacheLineLength (
133 VOID
134 );
135
136 UINT32
137 EFIAPI
138 Cp15IdCode (
139 VOID
140 );
141
142 UINT32
143 EFIAPI
144 Cp15CacheInfo (
145 VOID
146 );
147
148 VOID
149 EFIAPI
150 ArmInvalidateDataCache (
151 VOID
152 );
153
154 VOID
155 EFIAPI
156 ArmCleanInvalidateDataCache (
157 VOID
158 );
159
160 VOID
161 EFIAPI
162 ArmCleanDataCache (
163 VOID
164 );
165
166 VOID
167 EFIAPI
168 ArmInvalidateInstructionCache (
169 VOID
170 );
171
172 VOID
173 EFIAPI
174 ArmInvalidateDataCacheEntryByMVA (
175 IN UINTN Address
176 );
177
178 VOID
179 EFIAPI
180 ArmCleanDataCacheEntryByMVA (
181 IN UINTN Address
182 );
183
184 VOID
185 EFIAPI
186 ArmCleanInvalidateDataCacheEntryByMVA (
187 IN UINTN Address
188 );
189
190 VOID
191 EFIAPI
192 ArmEnableDataCache (
193 VOID
194 );
195
196 VOID
197 EFIAPI
198 ArmDisableDataCache (
199 VOID
200 );
201
202 VOID
203 EFIAPI
204 ArmEnableInstructionCache (
205 VOID
206 );
207
208 VOID
209 EFIAPI
210 ArmDisableInstructionCache (
211 VOID
212 );
213
214 VOID
215 EFIAPI
216 ArmEnableMmu (
217 VOID
218 );
219
220 VOID
221 EFIAPI
222 ArmDisableMmu (
223 VOID
224 );
225
226 VOID
227 EFIAPI
228 ArmEnableInterrupts (
229 VOID
230 );
231
232 UINTN
233 EFIAPI
234 ArmDisableInterrupts (
235 VOID
236 );
237
238 BOOLEAN
239 EFIAPI
240 ArmGetInterruptState (
241 VOID
242 );
243
244 VOID
245 EFIAPI
246 ArmInvalidateTlb (
247 VOID
248 );
249
250 VOID
251 EFIAPI
252 ArmSetDomainAccessControl (
253 IN UINT32 Domain
254 );
255
256 VOID
257 EFIAPI
258 ArmSetTranslationTableBaseAddress (
259 IN VOID *TranslationTableBase
260 );
261
262 VOID
263 EFIAPI
264 ArmConfigureMmu (
265 IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
266 OUT VOID **TranslationTableBase OPTIONAL,
267 OUT UINTN *TranslationTableSize OPTIONAL
268 );
269
270 VOID
271 EFIAPI
272 ArmSwitchProcessorMode (
273 IN ARM_PROCESSOR_MODE Mode
274 );
275
276 ARM_PROCESSOR_MODE
277 EFIAPI
278 ArmProcessorMode (
279 VOID
280 );
281
282 VOID
283 EFIAPI
284 ArmEnableBranchPrediction (
285 VOID
286 );
287
288 VOID
289 EFIAPI
290 ArmDisableBranchPrediction (
291 VOID
292 );
293
294 #endif // __ARM_LIB__