ArmPkg/Include/Library/ArmLib.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef __ARM_LIB__
  16 #define __ARM_LIB__
  17
  18 typedef enum {
  19   ARM_CACHE_TYPE_WRITE_BACK,
  20   ARM_CACHE_TYPE_UNKNOWN
  21 } ARM_CACHE_TYPE;
  22
  23 typedef enum {
  24   ARM_CACHE_ARCHITECTURE_UNIFIED,
  25   ARM_CACHE_ARCHITECTURE_SEPARATE,
  26   ARM_CACHE_ARCHITECTURE_UNKNOWN
  27 } ARM_CACHE_ARCHITECTURE;
  28
  29 typedef struct {
  30   ARM_CACHE_TYPE          Type;
  31   ARM_CACHE_ARCHITECTURE  Architecture;
  32   BOOLEAN                 DataCachePresent;
  33   UINTN                   DataCacheSize;
  34   UINTN                   DataCacheAssociativity;
  35   UINTN                   DataCacheLineLength;
  36   BOOLEAN                 InstructionCachePresent;
  37   UINTN                   InstructionCacheSize;
  38   UINTN                   InstructionCacheAssociativity;
  39   UINTN                   InstructionCacheLineLength;
  40 } ARM_CACHE_INFO;
  41
  42 typedef enum {
  43   ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED,
  44   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
  45   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
  46   ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
  47   ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED,
  48   ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK,
  49   ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH,
  50   ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE
  51 } ARM_MEMORY_REGION_ATTRIBUTES;
  52
  53 typedef struct {
  54   UINT32                        PhysicalBase;
  55   UINT32                        VirtualBase;
  56   UINT32                        Length;
  57   ARM_MEMORY_REGION_ATTRIBUTES  Attributes;
  58 } ARM_MEMORY_REGION_DESCRIPTOR;
  59
  60 typedef VOID (*CACHE_OPERATION)(VOID);
  61 typedef VOID (*LINE_OPERATION)(UINTN);
  62
  63 typedef enum {
  64   ARM_PROCESSOR_MODE_USER       = 0x10,
  65   ARM_PROCESSOR_MODE_FIQ        = 0x11,
  66   ARM_PROCESSOR_MODE_IRQ        = 0x12,
  67   ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
  68   ARM_PROCESSOR_MODE_ABORT      = 0x17,
  69   ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,
  70   ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,
  71   ARM_PROCESSOR_MODE_MASK       = 0x1F
  72 } ARM_PROCESSOR_MODE;
  73
  74 ARM_CACHE_TYPE
  75 EFIAPI
  76 ArmCacheType (
  77   VOID
  78   );
  79
  80 ARM_CACHE_ARCHITECTURE
  81 EFIAPI
  82 ArmCacheArchitecture (
  83   VOID
  84   );
  85
  86 VOID
  87 EFIAPI
  88 ArmCacheInformation (
  89   OUT ARM_CACHE_INFO  *CacheInfo
  90   );
  91
  92 BOOLEAN
  93 EFIAPI
  94 ArmDataCachePresent (
  95   VOID
  96   );
  97
  98 UINTN
  99 EFIAPI
 100 ArmDataCacheSize (
 101   VOID
 102   );
 103
 104 UINTN
 105 EFIAPI
 106 ArmDataCacheAssociativity (
 107   VOID
 108   );
 109
 110 UINTN
 111 EFIAPI
 112 ArmDataCacheLineLength (
 113   VOID
 114   );
 115
 116 BOOLEAN
 117 EFIAPI
 118 ArmInstructionCachePresent (
 119   VOID
 120   );
 121
 122 UINTN
 123 EFIAPI
 124 ArmInstructionCacheSize (
 125   VOID
 126   );
 127
 128 UINTN
 129 EFIAPI
 130 ArmInstructionCacheAssociativity (
 131   VOID
 132   );
 133
 134 UINTN
 135 EFIAPI
 136 ArmInstructionCacheLineLength (
 137   VOID
 138   );
 139
 140 UINT32
 141 EFIAPI
 142 Cp15IdCode (
 143   VOID
 144   );
 145
 146 UINT32
 147 EFIAPI
 148 Cp15CacheInfo (
 149   VOID
 150   );
 151
 152 BOOLEAN
 153 EFIAPI
 154 ArmIsMPCore (
 155   VOID
 156   );
 157
 158 VOID
 159 EFIAPI
 160 ArmInvalidateDataCache (
 161   VOID
 162   );
 163
 164
 165 VOID
 166 EFIAPI
 167 ArmCleanInvalidateDataCache (
 168   VOID
 169   );
 170
 171 VOID
 172 EFIAPI
 173 ArmCleanDataCache (
 174   VOID
 175   );
 176
 177 VOID
 178 EFIAPI
 179 ArmInvalidateInstructionCache (
 180   VOID
 181   );
 182
 183 VOID
 184 EFIAPI
 185 ArmInvalidateDataCacheEntryByMVA (
 186   IN  UINTN   Address
 187   );
 188
 189 VOID
 190 EFIAPI
 191 ArmCleanDataCacheEntryByMVA (
 192   IN  UINTN   Address
 193   );
 194
 195 VOID
 196 EFIAPI
 197 ArmCleanInvalidateDataCacheEntryByMVA (
 198   IN  UINTN   Address
 199   );
 200
 201 VOID
 202 EFIAPI
 203 ArmEnableDataCache (
 204   VOID
 205   );
 206
 207 VOID
 208 EFIAPI
 209 ArmDisableDataCache (
 210   VOID
 211   );
 212
 213 VOID
 214 EFIAPI
 215 ArmEnableInstructionCache (
 216   VOID
 217   );
 218
 219 VOID
 220 EFIAPI
 221 ArmDisableInstructionCache (
 222   VOID
 223   );
 224
 225 VOID
 226 EFIAPI
 227 ArmEnableMmu (
 228   VOID
 229   );
 230
 231 VOID
 232 EFIAPI
 233 ArmDisableMmu (
 234   VOID
 235   );
 236
 237 VOID
 238 EFIAPI
 239 ArmDisableCachesAndMmu (
 240   VOID
 241   );
 242
 243 VOID
 244 EFIAPI
 245 ArmEnableInterrupts (
 246   VOID
 247   );
 248
 249 UINTN
 250 EFIAPI
 251 ArmDisableInterrupts (
 252   VOID
 253   );
 254
 255 BOOLEAN
 256 EFIAPI
 257 ArmGetInterruptState (
 258   VOID
 259   );
 260
 261 VOID
 262 EFIAPI
 263 ArmEnableFiq (
 264   VOID
 265   );
 266
 267 UINTN
 268 EFIAPI
 269 ArmDisableFiq (
 270   VOID
 271   );
 272
 273 BOOLEAN
 274 EFIAPI
 275 ArmGetFiqState (
 276   VOID
 277   );
 278
 279 VOID
 280 EFIAPI
 281 ArmInvalidateTlb (
 282   VOID
 283   );
 284
 285 VOID
 286 EFIAPI
 287 ArmUpdateTranslationTableEntry (
 288   IN  VOID     *TranslationTableEntry,
 289   IN  VOID     *Mva
 290   );
 291
 292 VOID
 293 EFIAPI
 294 ArmSetDomainAccessControl (
 295   IN  UINT32  Domain
 296   );
 297
 298 VOID
 299 EFIAPI
 300 ArmSetTTBR0 (
 301   IN  VOID  *TranslationTableBase
 302   );
 303
 304 VOID *
 305 EFIAPI
 306 ArmGetTTBR0BaseAddress (
 307   VOID
 308   );
 309
 310 VOID
 311 EFIAPI
 312 ArmConfigureMmu (
 313   IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,
 314   OUT VOID                          **TranslationTableBase OPTIONAL,
 315   OUT UINTN                         *TranslationTableSize  OPTIONAL
 316   );
 317
 318 BOOLEAN
 319 EFIAPI
 320 ArmMmuEnabled (
 321   VOID
 322   );
 323
 324 VOID
 325 EFIAPI
 326 ArmSwitchProcessorMode (
 327   IN ARM_PROCESSOR_MODE Mode
 328   );
 329
 330 ARM_PROCESSOR_MODE
 331 EFIAPI
 332 ArmProcessorMode (
 333   VOID
 334   );
 335
 336 VOID
 337 EFIAPI
 338 ArmEnableBranchPrediction (
 339   VOID
 340   );
 341
 342 VOID
 343 EFIAPI
 344 ArmDisableBranchPrediction (
 345   VOID
 346   );
 347
 348 VOID
 349 EFIAPI
 350 ArmDataMemoryBarrier (
 351   VOID
 352   );
 353
 354 VOID
 355 EFIAPI
 356 ArmDataSyncronizationBarrier (
 357   VOID
 358   );
 359
 360 VOID
 361 EFIAPI
 362 ArmInstructionSynchronizationBarrier (
 363   VOID
 364   );
 365
 366
 367 #endif // __ARM_LIB__