ArmPkg/Include/Library/ArmLib.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
   5   Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>
   6
   7   SPDX-License-Identifier: BSD-2-Clause-Patent
   8
   9 **/
  10
  11 #ifndef ARM_LIB_H_
  12 #define ARM_LIB_H_
  13
  14 #include <Uefi/UefiBaseType.h>
  15
  16 #ifdef MDE_CPU_ARM
  17   #include <Chipset/ArmV7.h>
  18 #elif defined (MDE_CPU_AARCH64)
  19   #include <Chipset/AArch64.h>
  20 #else
  21   #error "Unknown chipset."
  22 #endif
  23
  24 #define EFI_MEMORY_CACHETYPE_MASK  (EFI_MEMORY_UC | EFI_MEMORY_WC |  \
  25                                      EFI_MEMORY_WT | EFI_MEMORY_WB | \
  26                                      EFI_MEMORY_UCE)
  27
  28 /**
  29  * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
  30  *
  31  * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
  32  * be used in Secure World to distinguished Secure to Non-Secure memory.
  33  */
  34 typedef enum {
  35   ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,
  36   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,
  37   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
  38   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,
  39
  40   // On some platforms, memory mapped flash region is designed as not supporting
  41   // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special
  42   // need.
  43   // Do NOT use below two attributes if you are not sure.
  44   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,
  45   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,
  46
  47   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
  48   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,
  49   ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
  50   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
  51 } ARM_MEMORY_REGION_ATTRIBUTES;
  52
  53 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr)  ((UINT32)(attr) & 1)
  54
  55 typedef struct {
  56   EFI_PHYSICAL_ADDRESS            PhysicalBase;
  57   EFI_VIRTUAL_ADDRESS             VirtualBase;
  58   UINT64                          Length;
  59   ARM_MEMORY_REGION_ATTRIBUTES    Attributes;
  60 } ARM_MEMORY_REGION_DESCRIPTOR;
  61
  62 typedef VOID (*CACHE_OPERATION)(
  63   VOID
  64   );
  65 typedef VOID (*LINE_OPERATION)(
  66   UINTN
  67   );
  68
  69 //
  70 // ARM Processor Mode
  71 //
  72 typedef enum {
  73   ARM_PROCESSOR_MODE_USER       = 0x10,
  74   ARM_PROCESSOR_MODE_FIQ        = 0x11,
  75   ARM_PROCESSOR_MODE_IRQ        = 0x12,
  76   ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
  77   ARM_PROCESSOR_MODE_ABORT      = 0x17,
  78   ARM_PROCESSOR_MODE_HYP        = 0x1A,
  79   ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,
  80   ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,
  81   ARM_PROCESSOR_MODE_MASK       = 0x1F
  82 } ARM_PROCESSOR_MODE;
  83
  84 //
  85 // ARM Cpu IDs
  86 //
  87 #define ARM_CPU_IMPLEMENTER_MASK      (0xFFU << 24)
  88 #define ARM_CPU_IMPLEMENTER_ARMLTD    (0x41U << 24)
  89 #define ARM_CPU_IMPLEMENTER_DEC       (0x44U << 24)
  90 #define ARM_CPU_IMPLEMENTER_MOT       (0x4DU << 24)
  91 #define ARM_CPU_IMPLEMENTER_QUALCOMM  (0x51U << 24)
  92 #define ARM_CPU_IMPLEMENTER_MARVELL   (0x56U << 24)
  93
  94 #define ARM_CPU_PRIMARY_PART_MASK       (0xFFF << 4)
  95 #define ARM_CPU_PRIMARY_PART_CORTEXA5   (0xC05 << 4)
  96 #define ARM_CPU_PRIMARY_PART_CORTEXA7   (0xC07 << 4)
  97 #define ARM_CPU_PRIMARY_PART_CORTEXA8   (0xC08 << 4)
  98 #define ARM_CPU_PRIMARY_PART_CORTEXA9   (0xC09 << 4)
  99 #define ARM_CPU_PRIMARY_PART_CORTEXA15  (0xC0F << 4)
 100
 101 //
 102 // ARM MP Core IDs
 103 //
 104 #define ARM_CORE_AFF0  0xFF
 105 #define ARM_CORE_AFF1  (0xFF << 8)
 106 #define ARM_CORE_AFF2  (0xFF << 16)
 107 #define ARM_CORE_AFF3  (0xFFULL << 32)
 108
 109 #define ARM_CORE_MASK     ARM_CORE_AFF0
 110 #define ARM_CLUSTER_MASK  ARM_CORE_AFF1
 111 #define GET_CORE_ID(MpId)            ((MpId) & ARM_CORE_MASK)
 112 #define GET_CLUSTER_ID(MpId)         (((MpId) & ARM_CLUSTER_MASK) >> 8)
 113 #define GET_MPID(ClusterId, CoreId)  (((ClusterId) << 8) | (CoreId))
 114 #define PRIMARY_CORE_ID  (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
 115
 116 /** Reads the CCSIDR register for the specified cache.
 117
 118   @param CSSELR The CSSELR cache selection register value.
 119
 120   @return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.
 121           Returns the contents of the CCSIDR register in AARCH32 mode.
 122 **/
 123 UINTN
 124 ReadCCSIDR (
 125   IN UINT32  CSSELR
 126   );
 127
 128 /** Reads the CCSIDR2 for the specified cache.
 129
 130   @param CSSELR The CSSELR cache selection register value
 131
 132   @return The contents of the CCSIDR2 register for the specified cache.
 133 **/
 134 UINT32
 135 ReadCCSIDR2 (
 136   IN UINT32  CSSELR
 137   );
 138
 139 /** Reads the Cache Level ID (CLIDR) register.
 140
 141   @return The contents of the CLIDR_EL1 register.
 142 **/
 143 UINT32
 144 ReadCLIDR (
 145   VOID
 146   );
 147
 148 UINTN
 149 EFIAPI
 150 ArmDataCacheLineLength (
 151   VOID
 152   );
 153
 154 UINTN
 155 EFIAPI
 156 ArmInstructionCacheLineLength (
 157   VOID
 158   );
 159
 160 UINTN
 161 EFIAPI
 162 ArmCacheWritebackGranule (
 163   VOID
 164   );
 165
 166 UINTN
 167 EFIAPI
 168 ArmIsArchTimerImplemented (
 169   VOID
 170   );
 171
 172 UINTN
 173 EFIAPI
 174 ArmCacheInfo (
 175   VOID
 176   );
 177
 178 BOOLEAN
 179 EFIAPI
 180 ArmIsMpCore (
 181   VOID
 182   );
 183
 184 VOID
 185 EFIAPI
 186 ArmInvalidateDataCache (
 187   VOID
 188   );
 189
 190 VOID
 191 EFIAPI
 192 ArmCleanInvalidateDataCache (
 193   VOID
 194   );
 195
 196 VOID
 197 EFIAPI
 198 ArmCleanDataCache (
 199   VOID
 200   );
 201
 202 VOID
 203 EFIAPI
 204 ArmInvalidateInstructionCache (
 205   VOID
 206   );
 207
 208 VOID
 209 EFIAPI
 210 ArmInvalidateDataCacheEntryByMVA (
 211   IN  UINTN  Address
 212   );
 213
 214 VOID
 215 EFIAPI
 216 ArmCleanDataCacheEntryToPoUByMVA (
 217   IN  UINTN  Address
 218   );
 219
 220 VOID
 221 EFIAPI
 222 ArmInvalidateInstructionCacheEntryToPoUByMVA (
 223   IN  UINTN  Address
 224   );
 225
 226 VOID
 227 EFIAPI
 228 ArmCleanDataCacheEntryByMVA (
 229   IN  UINTN  Address
 230   );
 231
 232 VOID
 233 EFIAPI
 234 ArmCleanInvalidateDataCacheEntryByMVA (
 235   IN  UINTN  Address
 236   );
 237
 238 VOID
 239 EFIAPI
 240 ArmEnableDataCache (
 241   VOID
 242   );
 243
 244 VOID
 245 EFIAPI
 246 ArmDisableDataCache (
 247   VOID
 248   );
 249
 250 VOID
 251 EFIAPI
 252 ArmEnableInstructionCache (
 253   VOID
 254   );
 255
 256 VOID
 257 EFIAPI
 258 ArmDisableInstructionCache (
 259   VOID
 260   );
 261
 262 VOID
 263 EFIAPI
 264 ArmEnableMmu (
 265   VOID
 266   );
 267
 268 VOID
 269 EFIAPI
 270 ArmDisableMmu (
 271   VOID
 272   );
 273
 274 VOID
 275 EFIAPI
 276 ArmEnableCachesAndMmu (
 277   VOID
 278   );
 279
 280 VOID
 281 EFIAPI
 282 ArmDisableCachesAndMmu (
 283   VOID
 284   );
 285
 286 VOID
 287 EFIAPI
 288 ArmEnableInterrupts (
 289   VOID
 290   );
 291
 292 UINTN
 293 EFIAPI
 294 ArmDisableInterrupts (
 295   VOID
 296   );
 297
 298 BOOLEAN
 299 EFIAPI
 300 ArmGetInterruptState (
 301   VOID
 302   );
 303
 304 VOID
 305 EFIAPI
 306 ArmEnableAsynchronousAbort (
 307   VOID
 308   );
 309
 310 UINTN
 311 EFIAPI
 312 ArmDisableAsynchronousAbort (
 313   VOID
 314   );
 315
 316 VOID
 317 EFIAPI
 318 ArmEnableIrq (
 319   VOID
 320   );
 321
 322 UINTN
 323 EFIAPI
 324 ArmDisableIrq (
 325   VOID
 326   );
 327
 328 VOID
 329 EFIAPI
 330 ArmEnableFiq (
 331   VOID
 332   );
 333
 334 UINTN
 335 EFIAPI
 336 ArmDisableFiq (
 337   VOID
 338   );
 339
 340 BOOLEAN
 341 EFIAPI
 342 ArmGetFiqState (
 343   VOID
 344   );
 345
 346 /**
 347  * Invalidate Data and Instruction TLBs
 348  */
 349 VOID
 350 EFIAPI
 351 ArmInvalidateTlb (
 352   VOID
 353   );
 354
 355 VOID
 356 EFIAPI
 357 ArmUpdateTranslationTableEntry (
 358   IN  VOID  *TranslationTableEntry,
 359   IN  VOID  *Mva
 360   );
 361
 362 VOID
 363 EFIAPI
 364 ArmSetDomainAccessControl (
 365   IN  UINT32  Domain
 366   );
 367
 368 VOID
 369 EFIAPI
 370 ArmSetTTBR0 (
 371   IN  VOID  *TranslationTableBase
 372   );
 373
 374 VOID
 375 EFIAPI
 376 ArmSetTTBCR (
 377   IN  UINT32  Bits
 378   );
 379
 380 VOID *
 381 EFIAPI
 382 ArmGetTTBR0BaseAddress (
 383   VOID
 384   );
 385
 386 BOOLEAN
 387 EFIAPI
 388 ArmMmuEnabled (
 389   VOID
 390   );
 391
 392 VOID
 393 EFIAPI
 394 ArmEnableBranchPrediction (
 395   VOID
 396   );
 397
 398 VOID
 399 EFIAPI
 400 ArmDisableBranchPrediction (
 401   VOID
 402   );
 403
 404 VOID
 405 EFIAPI
 406 ArmSetLowVectors (
 407   VOID
 408   );
 409
 410 VOID
 411 EFIAPI
 412 ArmSetHighVectors (
 413   VOID
 414   );
 415
 416 VOID
 417 EFIAPI
 418 ArmDataMemoryBarrier (
 419   VOID
 420   );
 421
 422 VOID
 423 EFIAPI
 424 ArmDataSynchronizationBarrier (
 425   VOID
 426   );
 427
 428 VOID
 429 EFIAPI
 430 ArmInstructionSynchronizationBarrier (
 431   VOID
 432   );
 433
 434 VOID
 435 EFIAPI
 436 ArmWriteVBar (
 437   IN  UINTN  VectorBase
 438   );
 439
 440 UINTN
 441 EFIAPI
 442 ArmReadVBar (
 443   VOID
 444   );
 445
 446 VOID
 447 EFIAPI
 448 ArmWriteAuxCr (
 449   IN  UINT32  Bit
 450   );
 451
 452 UINT32
 453 EFIAPI
 454 ArmReadAuxCr (
 455   VOID
 456   );
 457
 458 VOID
 459 EFIAPI
 460 ArmSetAuxCrBit (
 461   IN  UINT32  Bits
 462   );
 463
 464 VOID
 465 EFIAPI
 466 ArmUnsetAuxCrBit (
 467   IN  UINT32  Bits
 468   );
 469
 470 VOID
 471 EFIAPI
 472 ArmCallSEV (
 473   VOID
 474   );
 475
 476 VOID
 477 EFIAPI
 478 ArmCallWFE (
 479   VOID
 480   );
 481
 482 VOID
 483 EFIAPI
 484 ArmCallWFI (
 485
 486   VOID
 487   );
 488
 489 UINTN
 490 EFIAPI
 491 ArmReadMpidr (
 492   VOID
 493   );
 494
 495 UINTN
 496 EFIAPI
 497 ArmReadMidr (
 498   VOID
 499   );
 500
 501 UINT32
 502 EFIAPI
 503 ArmReadCpacr (
 504   VOID
 505   );
 506
 507 VOID
 508 EFIAPI
 509 ArmWriteCpacr (
 510   IN  UINT32  Access
 511   );
 512
 513 VOID
 514 EFIAPI
 515 ArmEnableVFP (
 516   VOID
 517   );
 518
 519 /**
 520   Get the Secure Configuration Register value
 521
 522   @return   Value read from the Secure Configuration Register
 523
 524 **/
 525 UINT32
 526 EFIAPI
 527 ArmReadScr (
 528   VOID
 529   );
 530
 531 /**
 532   Set the Secure Configuration Register
 533
 534   @param Value   Value to write to the Secure Configuration Register
 535
 536 **/
 537 VOID
 538 EFIAPI
 539 ArmWriteScr (
 540   IN  UINT32  Value
 541   );
 542
 543 UINT32
 544 EFIAPI
 545 ArmReadMVBar (
 546   VOID
 547   );
 548
 549 VOID
 550 EFIAPI
 551 ArmWriteMVBar (
 552   IN  UINT32  VectorMonitorBase
 553   );
 554
 555 UINT32
 556 EFIAPI
 557 ArmReadSctlr (
 558   VOID
 559   );
 560
 561 VOID
 562 EFIAPI
 563 ArmWriteSctlr (
 564   IN  UINT32  Value
 565   );
 566
 567 UINTN
 568 EFIAPI
 569 ArmReadHVBar (
 570   VOID
 571   );
 572
 573 VOID
 574 EFIAPI
 575 ArmWriteHVBar (
 576   IN  UINTN  HypModeVectorBase
 577   );
 578
 579 //
 580 // Helper functions for accessing CPU ACTLR
 581 //
 582
 583 UINTN
 584 EFIAPI
 585 ArmReadCpuActlr (
 586   VOID
 587   );
 588
 589 VOID
 590 EFIAPI
 591 ArmWriteCpuActlr (
 592   IN  UINTN  Val
 593   );
 594
 595 VOID
 596 EFIAPI
 597 ArmSetCpuActlrBit (
 598   IN  UINTN  Bits
 599   );
 600
 601 VOID
 602 EFIAPI
 603 ArmUnsetCpuActlrBit (
 604   IN  UINTN  Bits
 605   );
 606
 607 //
 608 // Accessors for the architected generic timer registers
 609 //
 610
 611 #define ARM_ARCH_TIMER_ENABLE   (1 << 0)
 612 #define ARM_ARCH_TIMER_IMASK    (1 << 1)
 613 #define ARM_ARCH_TIMER_ISTATUS  (1 << 2)
 614
 615 UINTN
 616 EFIAPI
 617 ArmReadCntFrq (
 618   VOID
 619   );
 620
 621 VOID
 622 EFIAPI
 623 ArmWriteCntFrq (
 624   UINTN  FreqInHz
 625   );
 626
 627 UINT64
 628 EFIAPI
 629 ArmReadCntPct (
 630   VOID
 631   );
 632
 633 UINTN
 634 EFIAPI
 635 ArmReadCntkCtl (
 636   VOID
 637   );
 638
 639 VOID
 640 EFIAPI
 641 ArmWriteCntkCtl (
 642   UINTN  Val
 643   );
 644
 645 UINTN
 646 EFIAPI
 647 ArmReadCntpTval (
 648   VOID
 649   );
 650
 651 VOID
 652 EFIAPI
 653 ArmWriteCntpTval (
 654   UINTN  Val
 655   );
 656
 657 UINTN
 658 EFIAPI
 659 ArmReadCntpCtl (
 660   VOID
 661   );
 662
 663 VOID
 664 EFIAPI
 665 ArmWriteCntpCtl (
 666   UINTN  Val
 667   );
 668
 669 UINTN
 670 EFIAPI
 671 ArmReadCntvTval (
 672   VOID
 673   );
 674
 675 VOID
 676 EFIAPI
 677 ArmWriteCntvTval (
 678   UINTN  Val
 679   );
 680
 681 UINTN
 682 EFIAPI
 683 ArmReadCntvCtl (
 684   VOID
 685   );
 686
 687 VOID
 688 EFIAPI
 689 ArmWriteCntvCtl (
 690   UINTN  Val
 691   );
 692
 693 UINT64
 694 EFIAPI
 695 ArmReadCntvCt (
 696   VOID
 697   );
 698
 699 UINT64
 700 EFIAPI
 701 ArmReadCntpCval (
 702   VOID
 703   );
 704
 705 VOID
 706 EFIAPI
 707 ArmWriteCntpCval (
 708   UINT64  Val
 709   );
 710
 711 UINT64
 712 EFIAPI
 713 ArmReadCntvCval (
 714   VOID
 715   );
 716
 717 VOID
 718 EFIAPI
 719 ArmWriteCntvCval (
 720   UINT64  Val
 721   );
 722
 723 UINT64
 724 EFIAPI
 725 ArmReadCntvOff (
 726   VOID
 727   );
 728
 729 VOID
 730 EFIAPI
 731 ArmWriteCntvOff (
 732   UINT64  Val
 733   );
 734
 735 UINTN
 736 EFIAPI
 737 ArmGetPhysicalAddressBits (
 738   VOID
 739   );
 740
 741 ///
 742 ///  ID Register Helper functions
 743 ///
 744
 745 /**
 746   Check whether the CPU supports the GIC system register interface (any version)
 747
 748   @return   Whether GIC System Register Interface is supported
 749
 750 **/
 751 BOOLEAN
 752 EFIAPI
 753 ArmHasGicSystemRegisters (
 754   VOID
 755   );
 756
 757 /** Checks if CCIDX is implemented.
 758
 759    @retval TRUE  CCIDX is implemented.
 760    @retval FALSE CCIDX is not implemented.
 761 **/
 762 BOOLEAN
 763 EFIAPI
 764 ArmHasCcidx (
 765   VOID
 766   );
 767
 768 #ifdef MDE_CPU_ARM
 769 ///
 770 /// AArch32-only ID Register Helper functions
 771 ///
 772
 773 /**
 774   Check whether the CPU supports the Security extensions
 775
 776   @return   Whether the Security extensions are implemented
 777
 778 **/
 779 BOOLEAN
 780 EFIAPI
 781 ArmHasSecurityExtensions (
 782   VOID
 783   );
 784
 785 #endif // MDE_CPU_ARM
 786
 787 #endif // ARM_LIB_H_