ArmPkg/Include/Library/ArmLib.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
   5   Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>
   6
   7   SPDX-License-Identifier: BSD-2-Clause-Patent
   8
   9 **/
  10
  11 #ifndef ARM_LIB_H_
  12 #define ARM_LIB_H_
  13
  14 #include <Uefi/UefiBaseType.h>
  15
  16 #ifdef MDE_CPU_ARM
  17   #include <Chipset/ArmV7.h>
  18 #elif defined(MDE_CPU_AARCH64)
  19   #include <Chipset/AArch64.h>
  20 #else
  21  #error "Unknown chipset."
  22 #endif
  23
  24 #define EFI_MEMORY_CACHETYPE_MASK   (EFI_MEMORY_UC | EFI_MEMORY_WC | \
  25                                      EFI_MEMORY_WT | EFI_MEMORY_WB | \
  26                                      EFI_MEMORY_UCE)
  27
  28 /**
  29  * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
  30  *
  31  * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
  32  * be used in Secure World to distinguished Secure to Non-Secure memory.
  33  */
  34 typedef enum {
  35   ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,
  36   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,
  37   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
  38   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,
  39
  40   // On some platforms, memory mapped flash region is designed as not supporting
  41   // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special
  42   // need.
  43   // Do NOT use below two attributes if you are not sure.
  44   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,
  45   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,
  46
  47   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
  48   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,
  49   ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
  50   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
  51 } ARM_MEMORY_REGION_ATTRIBUTES;
  52
  53 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
  54
  55 typedef struct {
  56   EFI_PHYSICAL_ADDRESS          PhysicalBase;
  57   EFI_VIRTUAL_ADDRESS           VirtualBase;
  58   UINT64                        Length;
  59   ARM_MEMORY_REGION_ATTRIBUTES  Attributes;
  60 } ARM_MEMORY_REGION_DESCRIPTOR;
  61
  62 typedef VOID (*CACHE_OPERATION)(VOID);
  63 typedef VOID (*LINE_OPERATION)(UINTN);
  64
  65 //
  66 // ARM Processor Mode
  67 //
  68 typedef enum {
  69   ARM_PROCESSOR_MODE_USER       = 0x10,
  70   ARM_PROCESSOR_MODE_FIQ        = 0x11,
  71   ARM_PROCESSOR_MODE_IRQ        = 0x12,
  72   ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
  73   ARM_PROCESSOR_MODE_ABORT      = 0x17,
  74   ARM_PROCESSOR_MODE_HYP        = 0x1A,
  75   ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,
  76   ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,
  77   ARM_PROCESSOR_MODE_MASK       = 0x1F
  78 } ARM_PROCESSOR_MODE;
  79
  80 //
  81 // ARM Cpu IDs
  82 //
  83 #define ARM_CPU_IMPLEMENTER_MASK          (0xFFU << 24)
  84 #define ARM_CPU_IMPLEMENTER_ARMLTD        (0x41U << 24)
  85 #define ARM_CPU_IMPLEMENTER_DEC           (0x44U << 24)
  86 #define ARM_CPU_IMPLEMENTER_MOT           (0x4DU << 24)
  87 #define ARM_CPU_IMPLEMENTER_QUALCOMM      (0x51U << 24)
  88 #define ARM_CPU_IMPLEMENTER_MARVELL       (0x56U << 24)
  89
  90 #define ARM_CPU_PRIMARY_PART_MASK         (0xFFF << 4)
  91 #define ARM_CPU_PRIMARY_PART_CORTEXA5     (0xC05 << 4)
  92 #define ARM_CPU_PRIMARY_PART_CORTEXA7     (0xC07 << 4)
  93 #define ARM_CPU_PRIMARY_PART_CORTEXA8     (0xC08 << 4)
  94 #define ARM_CPU_PRIMARY_PART_CORTEXA9     (0xC09 << 4)
  95 #define ARM_CPU_PRIMARY_PART_CORTEXA15    (0xC0F << 4)
  96
  97 //
  98 // ARM MP Core IDs
  99 //
 100 #define ARM_CORE_AFF0         0xFF
 101 #define ARM_CORE_AFF1         (0xFF << 8)
 102 #define ARM_CORE_AFF2         (0xFF << 16)
 103 #define ARM_CORE_AFF3         (0xFFULL << 32)
 104
 105 #define ARM_CORE_MASK         ARM_CORE_AFF0
 106 #define ARM_CLUSTER_MASK      ARM_CORE_AFF1
 107 #define GET_CORE_ID(MpId)     ((MpId) & ARM_CORE_MASK)
 108 #define GET_CLUSTER_ID(MpId)  (((MpId) & ARM_CLUSTER_MASK) >> 8)
 109 #define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))
 110 #define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
 111
 112 // The ARM Architecture Reference Manual for ARMv8-A defines up
 113 // to 7 levels of cache, L1 through L7.
 114 #define MAX_ARM_CACHE_LEVEL   7
 115
 116 UINTN
 117 EFIAPI
 118 ArmDataCacheLineLength (
 119   VOID
 120   );
 121
 122 UINTN
 123 EFIAPI
 124 ArmInstructionCacheLineLength (
 125   VOID
 126   );
 127
 128 UINTN
 129 EFIAPI
 130 ArmCacheWritebackGranule (
 131   VOID
 132   );
 133
 134 UINTN
 135 EFIAPI
 136 ArmIsArchTimerImplemented (
 137   VOID
 138   );
 139
 140 UINTN
 141 EFIAPI
 142 ArmCacheInfo (
 143   VOID
 144   );
 145
 146 BOOLEAN
 147 EFIAPI
 148 ArmIsMpCore (
 149   VOID
 150   );
 151
 152 VOID
 153 EFIAPI
 154 ArmInvalidateDataCache (
 155   VOID
 156   );
 157
 158
 159 VOID
 160 EFIAPI
 161 ArmCleanInvalidateDataCache (
 162   VOID
 163   );
 164
 165 VOID
 166 EFIAPI
 167 ArmCleanDataCache (
 168   VOID
 169   );
 170
 171 VOID
 172 EFIAPI
 173 ArmInvalidateInstructionCache (
 174   VOID
 175   );
 176
 177 VOID
 178 EFIAPI
 179 ArmInvalidateDataCacheEntryByMVA (
 180   IN  UINTN   Address
 181   );
 182
 183 VOID
 184 EFIAPI
 185 ArmCleanDataCacheEntryToPoUByMVA (
 186   IN  UINTN   Address
 187   );
 188
 189 VOID
 190 EFIAPI
 191 ArmInvalidateInstructionCacheEntryToPoUByMVA (
 192   IN  UINTN   Address
 193   );
 194
 195 VOID
 196 EFIAPI
 197 ArmCleanDataCacheEntryByMVA (
 198 IN  UINTN   Address
 199 );
 200
 201 VOID
 202 EFIAPI
 203 ArmCleanInvalidateDataCacheEntryByMVA (
 204   IN  UINTN   Address
 205   );
 206
 207 VOID
 208 EFIAPI
 209 ArmEnableDataCache (
 210   VOID
 211   );
 212
 213 VOID
 214 EFIAPI
 215 ArmDisableDataCache (
 216   VOID
 217   );
 218
 219 VOID
 220 EFIAPI
 221 ArmEnableInstructionCache (
 222   VOID
 223   );
 224
 225 VOID
 226 EFIAPI
 227 ArmDisableInstructionCache (
 228   VOID
 229   );
 230
 231 VOID
 232 EFIAPI
 233 ArmEnableMmu (
 234   VOID
 235   );
 236
 237 VOID
 238 EFIAPI
 239 ArmDisableMmu (
 240   VOID
 241   );
 242
 243 VOID
 244 EFIAPI
 245 ArmEnableCachesAndMmu (
 246   VOID
 247   );
 248
 249 VOID
 250 EFIAPI
 251 ArmDisableCachesAndMmu (
 252   VOID
 253   );
 254
 255 VOID
 256 EFIAPI
 257 ArmEnableInterrupts (
 258   VOID
 259   );
 260
 261 UINTN
 262 EFIAPI
 263 ArmDisableInterrupts (
 264   VOID
 265   );
 266
 267 BOOLEAN
 268 EFIAPI
 269 ArmGetInterruptState (
 270   VOID
 271   );
 272
 273 VOID
 274 EFIAPI
 275 ArmEnableAsynchronousAbort (
 276   VOID
 277   );
 278
 279 UINTN
 280 EFIAPI
 281 ArmDisableAsynchronousAbort (
 282   VOID
 283   );
 284
 285 VOID
 286 EFIAPI
 287 ArmEnableIrq (
 288   VOID
 289   );
 290
 291 UINTN
 292 EFIAPI
 293 ArmDisableIrq (
 294   VOID
 295   );
 296
 297 VOID
 298 EFIAPI
 299 ArmEnableFiq (
 300   VOID
 301   );
 302
 303 UINTN
 304 EFIAPI
 305 ArmDisableFiq (
 306   VOID
 307   );
 308
 309 BOOLEAN
 310 EFIAPI
 311 ArmGetFiqState (
 312   VOID
 313   );
 314
 315 /**
 316  * Invalidate Data and Instruction TLBs
 317  */
 318 VOID
 319 EFIAPI
 320 ArmInvalidateTlb (
 321   VOID
 322   );
 323
 324 VOID
 325 EFIAPI
 326 ArmUpdateTranslationTableEntry (
 327   IN  VOID     *TranslationTableEntry,
 328   IN  VOID     *Mva
 329   );
 330
 331 VOID
 332 EFIAPI
 333 ArmSetDomainAccessControl (
 334   IN  UINT32  Domain
 335   );
 336
 337 VOID
 338 EFIAPI
 339 ArmSetTTBR0 (
 340   IN  VOID  *TranslationTableBase
 341   );
 342
 343 VOID
 344 EFIAPI
 345 ArmSetTTBCR (
 346   IN  UINT32 Bits
 347   );
 348
 349 VOID *
 350 EFIAPI
 351 ArmGetTTBR0BaseAddress (
 352   VOID
 353   );
 354
 355 BOOLEAN
 356 EFIAPI
 357 ArmMmuEnabled (
 358   VOID
 359   );
 360
 361 VOID
 362 EFIAPI
 363 ArmEnableBranchPrediction (
 364   VOID
 365   );
 366
 367 VOID
 368 EFIAPI
 369 ArmDisableBranchPrediction (
 370   VOID
 371   );
 372
 373 VOID
 374 EFIAPI
 375 ArmSetLowVectors (
 376   VOID
 377   );
 378
 379 VOID
 380 EFIAPI
 381 ArmSetHighVectors (
 382   VOID
 383   );
 384
 385 VOID
 386 EFIAPI
 387 ArmDataMemoryBarrier (
 388   VOID
 389   );
 390
 391 VOID
 392 EFIAPI
 393 ArmDataSynchronizationBarrier (
 394   VOID
 395   );
 396
 397 VOID
 398 EFIAPI
 399 ArmInstructionSynchronizationBarrier (
 400   VOID
 401   );
 402
 403 VOID
 404 EFIAPI
 405 ArmWriteVBar (
 406   IN  UINTN   VectorBase
 407   );
 408
 409 UINTN
 410 EFIAPI
 411 ArmReadVBar (
 412   VOID
 413   );
 414
 415 VOID
 416 EFIAPI
 417 ArmWriteAuxCr (
 418   IN  UINT32    Bit
 419   );
 420
 421 UINT32
 422 EFIAPI
 423 ArmReadAuxCr (
 424   VOID
 425   );
 426
 427 VOID
 428 EFIAPI
 429 ArmSetAuxCrBit (
 430   IN  UINT32    Bits
 431   );
 432
 433 VOID
 434 EFIAPI
 435 ArmUnsetAuxCrBit (
 436   IN  UINT32    Bits
 437   );
 438
 439 VOID
 440 EFIAPI
 441 ArmCallSEV (
 442   VOID
 443   );
 444
 445 VOID
 446 EFIAPI
 447 ArmCallWFE (
 448   VOID
 449   );
 450
 451 VOID
 452 EFIAPI
 453 ArmCallWFI (
 454
 455   VOID
 456   );
 457
 458 UINTN
 459 EFIAPI
 460 ArmReadMpidr (
 461   VOID
 462   );
 463
 464 UINTN
 465 EFIAPI
 466 ArmReadMidr (
 467   VOID
 468   );
 469
 470 UINT32
 471 EFIAPI
 472 ArmReadCpacr (
 473   VOID
 474   );
 475
 476 VOID
 477 EFIAPI
 478 ArmWriteCpacr (
 479   IN  UINT32   Access
 480   );
 481
 482 VOID
 483 EFIAPI
 484 ArmEnableVFP (
 485   VOID
 486   );
 487
 488 /**
 489   Get the Secure Configuration Register value
 490
 491   @return   Value read from the Secure Configuration Register
 492
 493 **/
 494 UINT32
 495 EFIAPI
 496 ArmReadScr (
 497   VOID
 498   );
 499
 500 /**
 501   Set the Secure Configuration Register
 502
 503   @param Value   Value to write to the Secure Configuration Register
 504
 505 **/
 506 VOID
 507 EFIAPI
 508 ArmWriteScr (
 509   IN  UINT32   Value
 510   );
 511
 512 UINT32
 513 EFIAPI
 514 ArmReadMVBar (
 515   VOID
 516   );
 517
 518 VOID
 519 EFIAPI
 520 ArmWriteMVBar (
 521   IN  UINT32   VectorMonitorBase
 522   );
 523
 524 UINT32
 525 EFIAPI
 526 ArmReadSctlr (
 527   VOID
 528   );
 529
 530 VOID
 531 EFIAPI
 532 ArmWriteSctlr (
 533   IN  UINT32   Value
 534   );
 535
 536 UINTN
 537 EFIAPI
 538 ArmReadHVBar (
 539   VOID
 540   );
 541
 542 VOID
 543 EFIAPI
 544 ArmWriteHVBar (
 545   IN  UINTN   HypModeVectorBase
 546   );
 547
 548
 549 //
 550 // Helper functions for accessing CPU ACTLR
 551 //
 552
 553 UINTN
 554 EFIAPI
 555 ArmReadCpuActlr (
 556   VOID
 557   );
 558
 559 VOID
 560 EFIAPI
 561 ArmWriteCpuActlr (
 562   IN  UINTN Val
 563   );
 564
 565 VOID
 566 EFIAPI
 567 ArmSetCpuActlrBit (
 568   IN  UINTN    Bits
 569   );
 570
 571 VOID
 572 EFIAPI
 573 ArmUnsetCpuActlrBit (
 574   IN  UINTN    Bits
 575   );
 576
 577 //
 578 // Accessors for the architected generic timer registers
 579 //
 580
 581 #define ARM_ARCH_TIMER_ENABLE           (1 << 0)
 582 #define ARM_ARCH_TIMER_IMASK            (1 << 1)
 583 #define ARM_ARCH_TIMER_ISTATUS          (1 << 2)
 584
 585 UINTN
 586 EFIAPI
 587 ArmReadCntFrq (
 588   VOID
 589   );
 590
 591 VOID
 592 EFIAPI
 593 ArmWriteCntFrq (
 594   UINTN   FreqInHz
 595   );
 596
 597 UINT64
 598 EFIAPI
 599 ArmReadCntPct (
 600   VOID
 601   );
 602
 603 UINTN
 604 EFIAPI
 605 ArmReadCntkCtl (
 606   VOID
 607   );
 608
 609 VOID
 610 EFIAPI
 611 ArmWriteCntkCtl (
 612   UINTN   Val
 613   );
 614
 615 UINTN
 616 EFIAPI
 617 ArmReadCntpTval (
 618   VOID
 619   );
 620
 621 VOID
 622 EFIAPI
 623 ArmWriteCntpTval (
 624   UINTN   Val
 625   );
 626
 627 UINTN
 628 EFIAPI
 629 ArmReadCntpCtl (
 630   VOID
 631   );
 632
 633 VOID
 634 EFIAPI
 635 ArmWriteCntpCtl (
 636   UINTN   Val
 637   );
 638
 639 UINTN
 640 EFIAPI
 641 ArmReadCntvTval (
 642   VOID
 643   );
 644
 645 VOID
 646 EFIAPI
 647 ArmWriteCntvTval (
 648   UINTN   Val
 649   );
 650
 651 UINTN
 652 EFIAPI
 653 ArmReadCntvCtl (
 654   VOID
 655   );
 656
 657 VOID
 658 EFIAPI
 659 ArmWriteCntvCtl (
 660   UINTN   Val
 661   );
 662
 663 UINT64
 664 EFIAPI
 665 ArmReadCntvCt (
 666   VOID
 667   );
 668
 669 UINT64
 670 EFIAPI
 671 ArmReadCntpCval (
 672   VOID
 673   );
 674
 675 VOID
 676 EFIAPI
 677 ArmWriteCntpCval (
 678   UINT64   Val
 679   );
 680
 681 UINT64
 682 EFIAPI
 683 ArmReadCntvCval (
 684   VOID
 685   );
 686
 687 VOID
 688 EFIAPI
 689 ArmWriteCntvCval (
 690   UINT64   Val
 691   );
 692
 693 UINT64
 694 EFIAPI
 695 ArmReadCntvOff (
 696   VOID
 697   );
 698
 699 VOID
 700 EFIAPI
 701 ArmWriteCntvOff (
 702   UINT64   Val
 703   );
 704
 705 UINTN
 706 EFIAPI
 707 ArmGetPhysicalAddressBits (
 708   VOID
 709   );
 710
 711
 712 ///
 713 ///  ID Register Helper functions
 714 ///
 715
 716 /**
 717   Check whether the CPU supports the GIC system register interface (any version)
 718
 719   @return   Whether GIC System Register Interface is supported
 720
 721 **/
 722 BOOLEAN
 723 EFIAPI
 724 ArmHasGicSystemRegisters (
 725   VOID
 726   );
 727
 728 /** Checks if CCIDX is implemented.
 729
 730    @retval TRUE  CCIDX is implemented.
 731    @retval FALSE CCIDX is not implemented.
 732 **/
 733 BOOLEAN
 734 EFIAPI
 735 ArmHasCcidx (
 736   VOID
 737   );
 738
 739 #ifdef MDE_CPU_ARM
 740 ///
 741 /// AArch32-only ID Register Helper functions
 742 ///
 743 /**
 744   Check whether the CPU supports the Security extensions
 745
 746   @return   Whether the Security extensions are implemented
 747
 748 **/
 749 BOOLEAN
 750 EFIAPI
 751 ArmHasSecurityExtensions (
 752   VOID
 753   );
 754 #endif // MDE_CPU_ARM
 755
 756 #endif // ARM_LIB_H_