d59d1030fc77f7d417eb82b5eadc9bf63331f1c9
[mirror_edk2.git] / ArmPkg / Library / ArmDisassemblerLib / ThumbDisassembler.c
1 /** @file
2 Default exception handler
3
4 Copyright (c) 2008-2010, Apple Inc. All rights reserved.
5
6 All rights reserved. This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 **/
15
16 #include <Base.h>
17 #include <Library/BaseLib.h>
18 #include <Library/PrintLib.h>
19
20 extern CHAR8 *gReg[];
21
22 #define LOAD_STORE_FORMAT1 1
23 #define LOAD_STORE_FORMAT2 2
24 #define LOAD_STORE_FORMAT3 3
25 #define LOAD_STORE_FORMAT4 4
26 #define LOAD_STORE_MULTIPLE_FORMAT1 5
27 #define LOAD_STORE_MULTIPLE_FORMAT2 6
28 #define IMMED_8 7
29 #define CONDITIONAL_BRANCH 8
30 #define UNCONDITIONAL_BRANCH 9
31 #define UNCONDITIONAL_BRANCH_SHORT 109
32 #define BRANCH_EXCHANGE 10
33 #define DATA_FORMAT1 11
34 #define DATA_FORMAT2 12
35 #define DATA_FORMAT3 13
36 #define DATA_FORMAT4 14
37 #define DATA_FORMAT5 15
38 #define DATA_FORMAT6_SP 16
39 #define DATA_FORMAT6_PC 116
40 #define DATA_FORMAT7 17
41 #define DATA_FORMAT8 19
42 #define CPS_FORMAT 20
43 #define ENDIAN_FORMAT 21
44
45
46 typedef struct {
47 CHAR8 *Start;
48 UINT32 OpCode;
49 UINT32 Mask;
50 UINT32 AddressMode;
51 } THUMB_INSTRUCTIONS;
52
53 THUMB_INSTRUCTIONS gOpThumb[] = {
54 // Thumb 16-bit instrucitons
55 // Op Mask Format
56 { "ADC" , 0x4140, 0xffc0, DATA_FORMAT5 },
57
58 { "ADD" , 0x1c00, 0xfe00, DATA_FORMAT2 },
59 { "ADD" , 0x3000, 0xf800, DATA_FORMAT3 },
60 { "ADD" , 0x1800, 0xfe00, DATA_FORMAT1 },
61 { "ADD" , 0x4400, 0xff00, DATA_FORMAT8 }, // A8.6.9
62 { "ADD" , 0xa000, 0xf100, DATA_FORMAT6_PC },
63 { "ADD" , 0xa100, 0xf100, DATA_FORMAT6_SP },
64 { "ADD" , 0xb000, 0xff10, DATA_FORMAT7 },
65
66 { "AND" , 0x4000, 0xffc0, DATA_FORMAT5 },
67
68 { "ASR" , 0x1000, 0xf800, DATA_FORMAT4 },
69 { "ASR" , 0x4100, 0xffc0, DATA_FORMAT5 },
70
71 { "B" , 0xd000, 0xf000, CONDITIONAL_BRANCH },
72 { "B" , 0xe000, 0xf100, UNCONDITIONAL_BRANCH_SHORT },
73 { "BL" , 0xf100, 0xf100, UNCONDITIONAL_BRANCH },
74 { "BLX" , 0xe100, 0xf100, UNCONDITIONAL_BRANCH },
75 { "BLX" , 0x4780, 0xff80, BRANCH_EXCHANGE },
76 { "BX" , 0x4700, 0xff80, BRANCH_EXCHANGE },
77
78 { "BIC" , 0x4380, 0xffc0, DATA_FORMAT5 },
79 { "BKPT", 0xdf00, 0xff00, IMMED_8 },
80 { "CMN" , 0x42c0, 0xffc0, DATA_FORMAT5 },
81
82 { "CMP" , 0x2800, 0xf100, DATA_FORMAT3 },
83 { "CMP" , 0x4280, 0xffc0, DATA_FORMAT5 },
84 { "CMP" , 0x4500, 0xff00, DATA_FORMAT8 },
85
86 { "CPS" , 0xb660, 0xffe8, CPS_FORMAT },
87 { "CPY" , 0x4600, 0xff00, DATA_FORMAT8 },
88 { "EOR" , 0x4040, 0xffc0, DATA_FORMAT5 },
89
90 { "LDMIA" , 0xc800, 0xf800, LOAD_STORE_MULTIPLE_FORMAT1 },
91 { "LDR" , 0x6800, 0xf800, LOAD_STORE_FORMAT1 },
92 { "LDR" , 0x5800, 0xfe00, LOAD_STORE_FORMAT2 },
93 { "LDR" , 0x4800, 0xf800, LOAD_STORE_FORMAT3 },
94 { "LDR" , 0x9800, 0xf800, LOAD_STORE_FORMAT4 },
95 { "LDRB" , 0x7800, 0xf800, LOAD_STORE_FORMAT1 },
96 { "LDRB" , 0x5c00, 0xfe00, LOAD_STORE_FORMAT2 },
97 { "LDRH" , 0x8800, 0xf800, LOAD_STORE_FORMAT1 },
98 { "LDRH" , 0x7a00, 0xfe00, LOAD_STORE_FORMAT2 },
99 { "LDRSB" , 0x5600, 0xfe00, LOAD_STORE_FORMAT2 },
100 { "LDRSH" , 0x5e00, 0xfe00, LOAD_STORE_FORMAT2 },
101
102 { "LSL" , 0x0000, 0xf800, DATA_FORMAT4 },
103 { "LSL" , 0x4080, 0xffc0, DATA_FORMAT5 },
104 { "LSR" , 0x0001, 0xf800, DATA_FORMAT4 },
105 { "LSR" , 0x40c0, 0xffc0, DATA_FORMAT5 },
106
107 { "MOV" , 0x2000, 0xf800, DATA_FORMAT3 },
108 { "MOV" , 0x1c00, 0xffc0, DATA_FORMAT3 },
109 { "MOV" , 0x4600, 0xff00, DATA_FORMAT8 },
110
111 { "MUL" , 0x4340, 0xffc0, DATA_FORMAT5 },
112 { "MVN" , 0x41c0, 0xffc0, DATA_FORMAT5 },
113 { "NEG" , 0x4240, 0xffc0, DATA_FORMAT5 },
114 { "ORR" , 0x4180, 0xffc0, DATA_FORMAT5 },
115 { "POP" , 0xbc00, 0xfe00, LOAD_STORE_MULTIPLE_FORMAT2 },
116 { "POP" , 0xe400, 0xfe00, LOAD_STORE_MULTIPLE_FORMAT2 },
117
118 { "REV" , 0xba00, 0xffc0, DATA_FORMAT5 },
119 { "REV16" , 0xba40, 0xffc0, DATA_FORMAT5 },
120 { "REVSH" , 0xbac0, 0xffc0, DATA_FORMAT5 },
121
122 { "ROR" , 0x41c0, 0xffc0, DATA_FORMAT5 },
123 { "SBC" , 0x4180, 0xffc0, DATA_FORMAT5 },
124 { "SETEND" , 0xb650, 0xfff0, ENDIAN_FORMAT },
125
126 { "STMIA" , 0xc000, 0xf800, LOAD_STORE_MULTIPLE_FORMAT1 },
127 { "STR" , 0x6000, 0xf800, LOAD_STORE_FORMAT1 },
128 { "STR" , 0x5000, 0xfe00, LOAD_STORE_FORMAT2 },
129 { "STR" , 0x4000, 0xf800, LOAD_STORE_FORMAT3 },
130 { "STR" , 0x9000, 0xf800, LOAD_STORE_FORMAT4 },
131 { "STRB" , 0x7000, 0xf800, LOAD_STORE_FORMAT1 },
132 { "STRB" , 0x5800, 0xfe00, LOAD_STORE_FORMAT2 },
133 { "STRH" , 0x8000, 0xf800, LOAD_STORE_FORMAT1 },
134 { "STRH" , 0x5200, 0xfe00, LOAD_STORE_FORMAT2 },
135
136 { "SUB" , 0x1e00, 0xfe00, DATA_FORMAT2 },
137 { "SUB" , 0x3800, 0xf800, DATA_FORMAT3 },
138 { "SUB" , 0x1a00, 0xfe00, DATA_FORMAT1 },
139 { "SUB" , 0xb080, 0xff80, DATA_FORMAT7 },
140
141 { "SWI" , 0xdf00, 0xff00, IMMED_8 },
142 { "SXTB", 0xb240, 0xffc0, DATA_FORMAT5 },
143 { "SXTH", 0xb200, 0xffc0, DATA_FORMAT5 },
144 { "TST" , 0x4200, 0xffc0, DATA_FORMAT5 },
145 { "UXTB", 0xb2c0, 0xffc0, DATA_FORMAT5 },
146 { "UXTH", 0xb280, 0xffc0, DATA_FORMAT5 }
147 };
148
149 #if 0
150 THUMB_INSTRUCTIONS gOpThumb2[] = {
151 ,
152
153 // 32-bit Thumb instructions op1 01
154
155 // 1110 100x x0xx xxxx xxxx xxxx xxxx xxxx Load/store multiple
156 { "SRSDB", 0xe80dc000, 0xffdffff0, SRS_FORMAT }, // SRSDB<c> SP{!},#<mode>
157 { "SRS" , 0xe98dc000, 0xffdffff0, SRS_IA_FORMAT }, // SRS{IA}<c> SP{!},#<mode>
158 { "RFEDB", 0xe810c000, 0xffd0ffff, RFE_FORMAT }, // RFEDB<c> <Rn>{!}
159 { "RFE" , 0xe990c000, 0xffd0ffff, RFE_IA_FORMAT }, // RFE{IA}<c> <Rn>{!}
160
161 { "STM" , 0xe8800000, 0xffd00000, STM_FORMAT }, // STM<c>.W <Rn>{!},<registers>
162 { "LDM" , 0xe8900000, 0xffd00000, STM_FORMAT }, // LDR<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]
163 { "POP" , 0xe8bd0000, 0xffff2000, REGLIST_FORMAT }, // POP<c>.W <registers> >1 register
164 { "POP" , 0xf85d0b04, 0xffff0fff, RT_FORMAT }, // POP<c>.W <registers> 1 register
165
166 { "STMDB", 0xe9000000, 0xffd00000, STM_FORMAT }, // STMDB
167 { "PUSH" , 0xe8bd0000, 0xffffa000, REGLIST_FORMAT }, // PUSH<c>.W <registers> >1 register
168 { "PUSH" , 0xf84d0b04, 0xffff0fff, RT_FORMAT }, // PUSH<c>.W <registers> 1 register
169 { "LDMDB", 0xe9102000, 0xffd02000, STM_FORMAT }, // LDMDB<c> <Rn>{!},<registers>
170
171 // 1110 100x x1xx xxxx xxxx xxxx xxxx xxxx Load/store dual,
172 { "STREX" , 0xe0400000, 0xfff000f0, 3REG_IMM8_FORMAT }, // STREX<c> <Rd>,<Rt>,[<Rn>{,#<imm>}]
173 { "STREXB", 0xe8c00f40, 0xfff00ff0, 3REG_FORMAT }, // STREXB<c> <Rd>,<Rt>,[<Rn>]
174 { "STREXD", 0xe8c00070, 0xfff000f0, 4REG_FORMAT }, // STREXD<c> <Rd>,<Rt>,<Rt2>,[<Rn>]
175 { "STREXH", 0xe8c00f70, 0xfff00ff0, 3REG_FORMAT }, // STREXH<c> <Rd>,<Rt>,[<Rn>]
176 { "STRH", 0xf8c00000, 0xfff00000, 2REG_IMM8_FORMAT }, // STRH<c>.W <Rt>,[<Rn>{,#<imm12>}]
177 { "STRH", 0xf8200000, 0xfff00000, }, // STRH<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]
178
179
180
181 // 1110 101x xxxx xxxx xxxx xxxx xxxx xxxx Data-processing
182 // 1110 11xx xxxx xxxx xxxx xxxx xxxx xxxx Coprocessor
183
184 // 1111 0x0x xxxx xxxx 0xxx xxxx xxxx xxxx Data-processing modified immediate
185 // 1111 0x1x xxxx xxxx 0xxx xxxx xxxx xxxx Data-processing plain immediate
186 // 1111 0xxx xxxx xxxx 1xxx xxxx xxxx xxxx Branches
187
188 // 1111 1000 xxx0 xxxx xxxx xxxx xxxx xxxx Store single data item
189 // 1111 1001 xxx0 xxxx xxxx xxxx xxxx xxxx SIMD or load/store
190 // 1111 100x x001 xxxx xxxx xxxx xxxx xxxx Load byte, memory hints
191 // 1111 100x x011 xxxx xxxx xxxx xxxx xxxx Load halfword, memory hints
192 // 1111 100x x101 xxxx xxxx xxxx xxxx xxxx Load word
193
194 // 1111 1 010 xxxx xxxx xxxx xxxx xxxx xxxx Data-processing register
195 // 1111 1 011 0xxx xxxx xxxx xxxx xxxx xxxx Multiply
196 // 1111 1 011 1xxx xxxx xxxx xxxx xxxx xxxx Long Multiply
197 // 1111 1 1xx xxxx xxxx xxxx xxxx xxxx xxxx Coprocessor
198 };
199 #endif
200
201 CHAR8 mThumbMregListStr[4*15 + 1];
202
203 CHAR8 *
204 ThumbMRegList (
205 UINT32 OpCode
206 )
207 {
208 UINTN Index, Start, End;
209 CHAR8 *Str;
210 BOOLEAN First;
211
212 Str = mThumbMregListStr;
213 *Str = '\0';
214 AsciiStrCat (Str, "{");
215 // R0 - R7, PC
216 for (Index = 0, First = TRUE; Index <= 9; Index++) {
217 if ((OpCode & (1 << Index)) != 0) {
218 Start = End = Index;
219 for (Index++; ((OpCode & (1 << Index)) != 0) && (Index <= 9); Index++) {
220 End = Index;
221 }
222
223 if (!First) {
224 AsciiStrCat (Str, ",");
225 } else {
226 First = FALSE;
227 }
228
229 if (Start == End) {
230 AsciiStrCat (Str, gReg[(Start == 9)?15:Start]);
231 AsciiStrCat (Str, ", ");
232 } else {
233 AsciiStrCat (Str, gReg[Start]);
234 AsciiStrCat (Str, "-");
235 AsciiStrCat (Str, gReg[(End == 9)?15:End]);
236 }
237 }
238 }
239 if (First) {
240 AsciiStrCat (Str, "ERROR");
241 }
242 AsciiStrCat (Str, "}");
243
244 // BugBug: Make caller pass in buffer it is cleaner
245 return mThumbMregListStr;
246 }
247
248 UINT32
249 SignExtend (
250 IN UINT32 Data
251 )
252 {
253 return 0;
254 }
255
256 /**
257 Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to
258 point to next instructin.
259
260 We cheat and only decode instructions that access
261 memory. If the instruction is not found we dump the instruction in hex.
262
263 @param OpCodePtrPtr Pointer to pointer of ARM Thumb instruction to disassemble.
264 @param Buf Buffer to sprintf disassembly into.
265 @param Size Size of Buf in bytes.
266
267 **/
268 VOID
269 DisassembleThumbInstruction (
270 IN UINT16 **OpCodePtrPtr,
271 OUT CHAR8 *Buf,
272 OUT UINTN Size
273 )
274 {
275 UINT16 *OpCodePtr;
276 UINT16 OpCode;
277 UINT16 OpCode32;
278 UINT32 Index;
279 UINT32 Offset;
280 UINT16 Rd, Rn, Rm;
281 INT32 target_addr;
282 BOOLEAN H1, H2, imod;
283 UINT32 PC;
284
285 OpCodePtr = *OpCodePtrPtr;
286 OpCode = **OpCodePtrPtr;
287
288 // Thumb2 is a stream of 16-bit instructions not a 32-bit instruction.
289 OpCode32 = (OpCode << 16) | *(OpCodePtr + 1);
290
291 // These register names match branch form, but not others
292 Rd = OpCode & 0x7;
293 Rn = (OpCode >> 3) & 0x7;
294 Rm = (OpCode >> 6) & 0x7;
295 H1 = (OpCode & BIT7) != 0;
296 H2 = (OpCode & BIT6) != 0;
297 imod = (OpCode & BIT4) != 0;
298 PC = (UINT32)(UINTN)*OpCodePtr;
299
300 // Increment by the minimum instruction size, Thumb2 could be bigger
301 *OpCodePtrPtr += 1;
302
303 for (Index = 0; Index < sizeof (gOpThumb)/sizeof (THUMB_INSTRUCTIONS); Index++) {
304 if ((OpCode & gOpThumb[Index].Mask) == gOpThumb[Index].OpCode) {
305 Offset = AsciiSPrint (Buf, Size, "%a", gOpThumb[Index].Start);
306 switch (gOpThumb[Index].AddressMode) {
307 case LOAD_STORE_FORMAT1:
308 // A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]
309 AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, (OpCode >> 7) & 7, (OpCode >> 6) & 0x1f);
310 break;
311 case LOAD_STORE_FORMAT2:
312 // A6.5.1 <Rd>, [<Rn>, <Rm>]
313 AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d, r%d]", Rd, (OpCode >> 3) & 7, Rm);
314 break;
315 case LOAD_STORE_FORMAT3:
316 // A6.5.1 <Rd>, [PC, #<8_bit_offset>]
317 AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x]", (OpCode >> 8) & 7, OpCode & 0xff);
318 break;
319 case LOAD_STORE_FORMAT4:
320 // FIX ME!!!!!
321 AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [sp, #0x%x]", (OpCode >> 8) & 7, OpCode & 0xff);
322 break;
323
324 case LOAD_STORE_MULTIPLE_FORMAT1:
325 // <Rn>!, <registers>
326 AsciiSPrint (&Buf[Offset], Size - Offset, " r%d!, %a", (OpCode >> 8) & 7, ThumbMRegList (!BIT8 & OpCode));
327 break;
328 case LOAD_STORE_MULTIPLE_FORMAT2:
329 // <Rn>!, <registers>
330 // BIT8 is PC
331 AsciiSPrint (&Buf[Offset], Size - Offset, " r%d!, %a", (OpCode >> 8) & 7, ThumbMRegList (OpCode));
332 break;
333
334 case IMMED_8:
335 // A6.7 <immed_8>
336 AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%x", OpCode & 0xff);
337 break;
338
339 case CONDITIONAL_BRANCH:
340 // A6.3.1 B<cond> <target_address>
341 AsciiSPrint (&Buf[Offset], Size - Offset, "%a 0x%04x", PC + 4 + SignExtend ((OpCode & 0xff) << 1));
342 break;
343 case UNCONDITIONAL_BRANCH_SHORT:
344 // A6.3.2 B <target_address>
345 AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend ((OpCode & 0x3ff) << 1));
346 break;
347 case UNCONDITIONAL_BRANCH:
348 // A6.3.2 BL|BLX <target_address> ; Produces two 16-bit instructions
349 target_addr = *(OpCodePtr - 1);
350 if ((target_addr & 0xf800) == 0xf000) {
351 target_addr = ((target_addr & 0x3ff) << 12) | (OpCode & 0x3ff);
352 } else {
353 target_addr = OpCode & 0x3ff;
354 }
355 // PC + 2 +/- target_addr
356 AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 2 + SignExtend (target_addr));
357 break;
358 case BRANCH_EXCHANGE:
359 // A6.3.3 BX|BLX <Rm>
360 AsciiSPrint (&Buf[Offset], Size - Offset, " r%d", gReg[Rn | (H2 ? 8:0)]);
361 break;
362
363 case DATA_FORMAT1:
364 // A6.4.3 <Rd>, <Rn>, <Rm>
365 AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, r%d", Rd, Rn, Rm);
366 break;
367 case DATA_FORMAT2:
368 // A6.4.3 <Rd>, <Rn>, #3_bit_immed
369 AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rd, Rn, Rm);
370 break;
371 case DATA_FORMAT3:
372 // A6.4.3 <Rd>|<Rn>, #8_bit_immed
373 AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", (OpCode >> 8) & 0x7, OpCode & 0xff);
374 break;
375 case DATA_FORMAT4:
376 // A6.4.3 <Rd>|<Rm>, #immed_5
377 AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rn, Rd, (OpCode >> 6) & 0x1f);
378 break;
379 case DATA_FORMAT5:
380 // A6.4.3 <Rd>|<Rm>, <Rm>|<Rs>
381 AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d", Rd, Rn);
382 break;
383 case DATA_FORMAT6_SP:
384 // A6.4.3 <Rd>, <reg>, #<8_Bit_immed>
385 AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, sp, 0x%x", (OpCode >> 8) & 7, OpCode & 0xff);
386 break;
387 case DATA_FORMAT6_PC:
388 // A6.4.3 <Rd>, <reg>, #<8_Bit_immed>
389 AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, pc, 0x%x", (OpCode >> 8) & 7, OpCode & 0xff);
390 break;
391 case DATA_FORMAT7:
392 // A6.4.3 SP, SP, #<7_Bit_immed>
393 AsciiSPrint (&Buf[Offset], Size - Offset, " sp, sp 0x%x", (OpCode & 0x7f)*4);
394 break;
395 case DATA_FORMAT8:
396 // A6.4.3 <Rd>|<Rn>, <Rm>
397 AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1 ? 8:0)], gReg[Rn | (H2 ? 8:0)]);
398 break;
399
400 case CPS_FORMAT:
401 // A7.1.24
402 AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", imod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a", ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f");
403 break;
404
405 case ENDIAN_FORMAT:
406 // A7.1.24
407 AsciiSPrint (&Buf[Offset], Size - Offset, " %a", (OpCode & BIT3) == 0 ? "LE":"BE");
408 break;
409 }
410 }
411 }
412 #if 0
413 // Thumb2 are 32-bit instructions
414 *OpCodePtrPtr += 1;
415 for (Index = 0; Index < sizeof (gOpThumb2)/sizeof (THUMB_INSTRUCTIONS); Index++) {
416 if ((OpCode32 & gOpThumb2[Index].Mask) == gOpThumb2[Index].OpCode) {
417 }
418 }
419 #endif
420 // Unknown instruction is 16-bits
421 *OpCodePtrPtr -= 1;
422 AsciiSPrint (Buf, Size, "0x%04x", OpCode);
423 }
424
425
426
427 VOID
428 DisassembleArmInstruction (
429 IN UINT32 **OpCodePtr,
430 OUT CHAR8 *Buf,
431 OUT UINTN Size
432 );
433
434
435 /**
436 Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to
437 point to next instructin.
438
439 We cheat and only decode instructions that access
440 memory. If the instruction is not found we dump the instruction in hex.
441
442 @param OpCodePtrPtr Pointer to pointer of ARM Thumb instruction to disassemble.
443 @param Thumb TRUE for Thumb(2), FALSE for ARM instruction stream
444 @param Buf Buffer to sprintf disassembly into.
445 @param Size Size of Buf in bytes.
446
447 **/
448 VOID
449 DisassembleInstruction (
450 IN UINT8 **OpCodePtr,
451 IN BOOLEAN Thumb,
452 OUT CHAR8 *Buf,
453 OUT UINTN Size
454 )
455 {
456 if (Thumb) {
457 DisassembleThumbInstruction ((UINT16 **)OpCodePtr, Buf, Size);
458 } else {
459 DisassembleArmInstruction ((UINT32 **)OpCodePtr, Buf, Size);
460 }
461 }
462