2 Default exception handler
4 Copyright (c) 2008-2010, Apple Inc. All rights reserved.
6 All rights reserved. This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 #include <Library/BaseLib.h>
18 #include <Library/PrintLib.h>
20 extern CHAR8
*gCondition
[];
24 #define LOAD_STORE_FORMAT1 1
25 #define LOAD_STORE_FORMAT2 2
26 #define LOAD_STORE_FORMAT3 3
27 #define LOAD_STORE_FORMAT4 4
28 #define LOAD_STORE_MULTIPLE_FORMAT1 5
30 #define POP_FORMAT 106
32 #define CONDITIONAL_BRANCH 8
33 #define UNCONDITIONAL_BRANCH 9
34 #define UNCONDITIONAL_BRANCH_SHORT 109
35 #define BRANCH_EXCHANGE 10
36 #define DATA_FORMAT1 11
37 #define DATA_FORMAT2 12
38 #define DATA_FORMAT3 13
39 #define DATA_FORMAT4 14
40 #define DATA_FORMAT5 15
41 #define DATA_FORMAT6_SP 16
42 #define DATA_FORMAT6_PC 116
43 #define DATA_FORMAT7 17
44 #define DATA_FORMAT8 19
46 #define ENDIAN_FORMAT 21
60 THUMB_INSTRUCTIONS gOpThumb
[] = {
61 // Thumb 16-bit instrucitons
63 { "ADC" , 0x4140, 0xffc0, DATA_FORMAT5
},
65 { "ADD" , 0x1c00, 0xfe00, DATA_FORMAT2
},
66 { "ADD" , 0x3000, 0xf800, DATA_FORMAT3
},
67 { "ADD" , 0x1800, 0xfe00, DATA_FORMAT1
},
68 { "ADD" , 0x4400, 0xff00, DATA_FORMAT8
}, // A8.6.9
69 { "ADD" , 0xa000, 0xf100, DATA_FORMAT6_PC
},
70 { "ADD" , 0xa800, 0xf800, DATA_FORMAT6_SP
},
71 { "ADD" , 0xb000, 0xff80, DATA_FORMAT7
},
73 { "AND" , 0x4000, 0xffc0, DATA_FORMAT5
},
75 { "ASR" , 0x1000, 0xf800, DATA_FORMAT4
},
76 { "ASR" , 0x4100, 0xffc0, DATA_FORMAT5
},
78 { "B" , 0xd000, 0xf000, CONDITIONAL_BRANCH
},
79 { "B" , 0xe000, 0xf800, UNCONDITIONAL_BRANCH_SHORT
},
80 { "BLX" , 0x4780, 0xff80, BRANCH_EXCHANGE
},
81 { "BX" , 0x4700, 0xff87, BRANCH_EXCHANGE
},
83 { "BIC" , 0x4380, 0xffc0, DATA_FORMAT5
},
84 { "BKPT", 0xdf00, 0xff00, IMMED_8
},
85 { "CMN" , 0x42c0, 0xffc0, DATA_FORMAT5
},
87 { "CMP" , 0x2800, 0xf800, DATA_FORMAT3
},
88 { "CMP" , 0x4280, 0xffc0, DATA_FORMAT5
},
89 { "CMP" , 0x4500, 0xff00, DATA_FORMAT8
},
91 { "CPS" , 0xb660, 0xffe8, CPS_FORMAT
},
92 { "MOV" , 0x4600, 0xff00, DATA_FORMAT8
},
93 { "EOR" , 0x4040, 0xffc0, DATA_FORMAT5
},
95 { "LDMIA" , 0xc800, 0xf800, LOAD_STORE_MULTIPLE_FORMAT1
},
96 { "LDR" , 0x6800, 0xf800, LOAD_STORE_FORMAT1
},
97 { "LDR" , 0x5800, 0xfe00, LOAD_STORE_FORMAT2
},
98 { "LDR" , 0x4800, 0xf800, LOAD_STORE_FORMAT3
},
99 { "LDR" , 0x9800, 0xf800, LOAD_STORE_FORMAT4
},
100 { "LDRB" , 0x7800, 0xf800, LOAD_STORE_FORMAT1
},
101 { "LDRB" , 0x5c00, 0xfe00, LOAD_STORE_FORMAT2
},
102 { "LDRH" , 0x8800, 0xf800, LOAD_STORE_FORMAT1
},
103 { "LDRH" , 0x7a00, 0xfe00, LOAD_STORE_FORMAT2
},
104 { "LDRSB" , 0x5600, 0xfe00, LOAD_STORE_FORMAT2
},
105 { "LDRSH" , 0x5e00, 0xfe00, LOAD_STORE_FORMAT2
},
107 { "MOVS", 0x0000, 0xffc0, DATA_FORMAT5
}, // LSL with imm5 == 0 is a MOVS, so this must go before LSL
108 { "LSL" , 0x0000, 0xf800, DATA_FORMAT4
},
109 { "LSL" , 0x4080, 0xffc0, DATA_FORMAT5
},
110 { "LSR" , 0x0001, 0xf800, DATA_FORMAT4
},
111 { "LSR" , 0x40c0, 0xffc0, DATA_FORMAT5
},
113 { "MOVS", 0x2000, 0xf800, DATA_FORMAT3
},
114 { "MOV" , 0x1c00, 0xffc0, DATA_FORMAT3
},
115 { "MOV" , 0x4600, 0xff00, DATA_FORMAT8
},
117 { "MUL" , 0x4340, 0xffc0, DATA_FORMAT5
},
118 { "MVN" , 0x41c0, 0xffc0, DATA_FORMAT5
},
119 { "NEG" , 0x4240, 0xffc0, DATA_FORMAT5
},
120 { "ORR" , 0x4180, 0xffc0, DATA_FORMAT5
},
121 { "POP" , 0xbc00, 0xfe00, POP_FORMAT
},
122 { "PUSH", 0xb400, 0xfe00, PUSH_FORMAT
},
124 { "REV" , 0xba00, 0xffc0, DATA_FORMAT5
},
125 { "REV16" , 0xba40, 0xffc0, DATA_FORMAT5
},
126 { "REVSH" , 0xbac0, 0xffc0, DATA_FORMAT5
},
128 { "ROR" , 0x41c0, 0xffc0, DATA_FORMAT5
},
129 { "SBC" , 0x4180, 0xffc0, DATA_FORMAT5
},
130 { "SETEND" , 0xb650, 0xfff0, ENDIAN_FORMAT
},
132 { "STMIA" , 0xc000, 0xf800, LOAD_STORE_MULTIPLE_FORMAT1
},
133 { "STR" , 0x6000, 0xf800, LOAD_STORE_FORMAT1
},
134 { "STR" , 0x5000, 0xfe00, LOAD_STORE_FORMAT2
},
135 { "STR" , 0x4000, 0xf800, LOAD_STORE_FORMAT3
},
136 { "STR" , 0x9000, 0xf800, LOAD_STORE_FORMAT4
},
137 { "STRB" , 0x7000, 0xf800, LOAD_STORE_FORMAT1
},
138 { "STRB" , 0x5800, 0xfe00, LOAD_STORE_FORMAT2
},
139 { "STRH" , 0x8000, 0xf800, LOAD_STORE_FORMAT1
},
140 { "STRH" , 0x5200, 0xfe00, LOAD_STORE_FORMAT2
},
142 { "SUB" , 0x1e00, 0xfe00, DATA_FORMAT2
},
143 { "SUB" , 0x3800, 0xf800, DATA_FORMAT3
},
144 { "SUB" , 0x1a00, 0xfe00, DATA_FORMAT1
},
145 { "SUB" , 0xb080, 0xff80, DATA_FORMAT7
},
147 { "SWI" , 0xdf00, 0xff00, IMMED_8
},
148 { "SXTB", 0xb240, 0xffc0, DATA_FORMAT5
},
149 { "SXTH", 0xb200, 0xffc0, DATA_FORMAT5
},
150 { "TST" , 0x4200, 0xffc0, DATA_FORMAT5
},
151 { "UXTB", 0xb2c0, 0xffc0, DATA_FORMAT5
},
152 { "UXTH", 0xb280, 0xffc0, DATA_FORMAT5
}
155 THUMB_INSTRUCTIONS gOpThumb2
[] = {
156 { "B", 0xf0008000, 0xf800d000, B_T3
},
157 { "B", 0xf0009000, 0xf800d000, B_T4
},
158 { "BL", 0xf000d000, 0xf800d000, B_T4
},
159 { "BLX", 0xf000c000, 0xf800d000, BL_T2
}
160 // ADD POP PUSH STR(B)(D) LDR(B)(D) EOR MOV ADDS SUBS STM
163 // 32-bit Thumb instructions op1 01
165 // 1110 100x x0xx xxxx xxxx xxxx xxxx xxxx Load/store multiple
166 { "SRSDB", 0xe80dc000, 0xffdffff0, SRS_FORMAT
}, // SRSDB<c> SP{!},#<mode>
167 { "SRS" , 0xe98dc000, 0xffdffff0, SRS_IA_FORMAT
}, // SRS{IA}<c> SP{!},#<mode>
168 { "RFEDB", 0xe810c000, 0xffd0ffff, RFE_FORMAT
}, // RFEDB<c> <Rn>{!}
169 { "RFE" , 0xe990c000, 0xffd0ffff, RFE_IA_FORMAT
}, // RFE{IA}<c> <Rn>{!}
171 { "STM" , 0xe8800000, 0xffd00000, STM_FORMAT
}, // STM<c>.W <Rn>{!},<registers>
172 { "LDM" , 0xe8900000, 0xffd00000, STM_FORMAT
}, // LDR<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]
173 { "POP" , 0xe8bd0000, 0xffff2000, REGLIST_FORMAT
}, // POP<c>.W <registers> >1 register
174 { "POP" , 0xf85d0b04, 0xffff0fff, RT_FORMAT
}, // POP<c>.W <registers> 1 register
176 { "STMDB", 0xe9000000, 0xffd00000, STM_FORMAT
}, // STMDB
177 { "PUSH" , 0xe8bd0000, 0xffffa000, REGLIST_FORMAT
}, // PUSH<c>.W <registers> >1 register
178 { "PUSH" , 0xf84d0b04, 0xffff0fff, RT_FORMAT
}, // PUSH<c>.W <registers> 1 register
179 { "LDMDB", 0xe9102000, 0xffd02000, STM_FORMAT
}, // LDMDB<c> <Rn>{!},<registers>
181 // 1110 100x x1xx xxxx xxxx xxxx xxxx xxxx Load/store dual,
182 { "STREX" , 0xe0400000, 0xfff000f0, 3REG_IMM8_FORMAT
}, // STREX<c> <Rd>,<Rt>,[<Rn>{,#<imm>}]
183 { "STREXB", 0xe8c00f40, 0xfff00ff0, 3REG_FORMAT
}, // STREXB<c> <Rd>,<Rt>,[<Rn>]
184 { "STREXD", 0xe8c00070, 0xfff000f0, 4REG_FORMAT
}, // STREXD<c> <Rd>,<Rt>,<Rt2>,[<Rn>]
185 { "STREXH", 0xe8c00f70, 0xfff00ff0, 3REG_FORMAT
}, // STREXH<c> <Rd>,<Rt>,[<Rn>]
186 { "STRH", 0xf8c00000, 0xfff00000, 2REG_IMM8_FORMAT
}, // STRH<c>.W <Rt>,[<Rn>{,#<imm12>}]
187 { "STRH", 0xf8200000, 0xfff00000, }, // STRH<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]
191 // 1110 101x xxxx xxxx xxxx xxxx xxxx xxxx Data-processing
192 // 1110 11xx xxxx xxxx xxxx xxxx xxxx xxxx Coprocessor
194 // 1111 0x0x xxxx xxxx 0xxx xxxx xxxx xxxx Data-processing modified immediate
195 // 1111 0x1x xxxx xxxx 0xxx xxxx xxxx xxxx Data-processing plain immediate
196 // 1111 0xxx xxxx xxxx 1xxx xxxx xxxx xxxx Branches
198 // 1111 1000 xxx0 xxxx xxxx xxxx xxxx xxxx Store single data item
199 // 1111 1001 xxx0 xxxx xxxx xxxx xxxx xxxx SIMD or load/store
200 // 1111 100x x001 xxxx xxxx xxxx xxxx xxxx Load byte, memory hints
201 // 1111 100x x011 xxxx xxxx xxxx xxxx xxxx Load halfword, memory hints
202 // 1111 100x x101 xxxx xxxx xxxx xxxx xxxx Load word
204 // 1111 1 010 xxxx xxxx xxxx xxxx xxxx xxxx Data-processing register
205 // 1111 1 011 0xxx xxxx xxxx xxxx xxxx xxxx Multiply
206 // 1111 1 011 1xxx xxxx xxxx xxxx xxxx xxxx Long Multiply
207 // 1111 1 1xx xxxx xxxx xxxx xxxx xxxx xxxx Coprocessor
211 CHAR8 mThumbMregListStr
[4*15 + 1];
218 UINTN Index
, Start
, End
;
222 Str
= mThumbMregListStr
;
224 AsciiStrCat (Str
, "{");
226 for (Index
= 0, First
= TRUE
; Index
<= 15; Index
++) {
227 if ((RegBitMask
& (1 << Index
)) != 0) {
229 for (Index
++; ((RegBitMask
& (1 << Index
)) != 0) && (Index
<= 9); Index
++) {
234 AsciiStrCat (Str
, ",");
240 AsciiStrCat (Str
, gReg
[Start
]);
242 AsciiStrCat (Str
, gReg
[Start
]);
243 AsciiStrCat (Str
, "-");
244 AsciiStrCat (Str
, gReg
[End
]);
249 AsciiStrCat (Str
, "ERROR");
251 AsciiStrCat (Str
, "}");
253 // BugBug: Make caller pass in buffer it is cleaner
254 return mThumbMregListStr
;
263 if (((Data
& TopBit
) == 0) || (TopBit
== BIT31
)) {
270 } while ((TopBit
& BIT31
) != BIT31
);
276 Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to
277 point to next instructin.
279 We cheat and only decode instructions that access
280 memory. If the instruction is not found we dump the instruction in hex.
282 @param OpCodePtrPtr Pointer to pointer of ARM Thumb instruction to disassemble.
283 @param Buf Buffer to sprintf disassembly into.
284 @param Size Size of Buf in bytes.
285 @param Extended TRUE dump hex for instruction too.
289 DisassembleThumbInstruction (
290 IN UINT16
**OpCodePtrPtr
,
302 BOOLEAN H1
, H2
, imod
;
307 OpCodePtr
= *OpCodePtrPtr
;
308 OpCode
= **OpCodePtrPtr
;
310 // Thumb2 is a stream of 16-bit instructions not a 32-bit instruction.
311 OpCode32
= (((UINT32
)OpCode
) << 16) | *(OpCodePtr
+ 1);
313 // These register names match branch form, but not others
315 Rn
= (OpCode
>> 3) & 0x7;
316 Rm
= (OpCode
>> 6) & 0x7;
317 H1
= (OpCode
& BIT7
) != 0;
318 H2
= (OpCode
& BIT6
) != 0;
319 imod
= (OpCode
& BIT4
) != 0;
320 PC
= (UINT32
)(UINTN
)OpCodePtr
;
322 // Increment by the minimum instruction size, Thumb2 could be bigger
325 for (Index
= 0; Index
< sizeof (gOpThumb
)/sizeof (THUMB_INSTRUCTIONS
); Index
++) {
326 if ((OpCode
& gOpThumb
[Index
].Mask
) == gOpThumb
[Index
].OpCode
) {
328 Offset
= AsciiSPrint (Buf
, Size
, "0x%04x %-6a", OpCode
, gOpThumb
[Index
].Start
);
330 Offset
= AsciiSPrint (Buf
, Size
, "%-6a", gOpThumb
[Index
].Start
);
332 switch (gOpThumb
[Index
].AddressMode
) {
333 case LOAD_STORE_FORMAT1
:
334 // A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]
335 AsciiSPrint (&Buf
[Offset
], Size
- Offset
, " r%d, [r%d #0x%x]", Rd
, Rn
, (OpCode
>> 4) & 0x7c);
337 case LOAD_STORE_FORMAT2
:
338 // A6.5.1 <Rd>, [<Rn>, <Rm>]
339 AsciiSPrint (&Buf
[Offset
], Size
- Offset
, " r%d, [r%d, r%d]", Rd
, Rn
, Rm
);
341 case LOAD_STORE_FORMAT3
:
342 // A6.5.1 <Rd>, [PC, #<8_bit_offset>]
343 Target
= (OpCode
& 0xff) << 2;
344 AsciiSPrint (&Buf
[Offset
], Size
- Offset
, " r%d, [pc, #0x%x] ;0x%08x", (OpCode
>> 8) & 7, Target
, PC
+ 4 + Target
);
346 case LOAD_STORE_FORMAT4
:
348 Target
= (OpCode
& 0xff) << 2;
349 AsciiSPrint (&Buf
[Offset
], Size
- Offset
, " r%d, [sp, #0x%x]", (OpCode
>> 8) & 7, Target
, PC
+ 3 + Target
);
352 case LOAD_STORE_MULTIPLE_FORMAT1
:
354 AsciiSPrint (&Buf
[Offset
], Size
- Offset
, " r%d!, %a", (OpCode
>> 8) & 7, ThumbMRegList (OpCode
& 0xff));
359 AsciiSPrint (&Buf
[Offset
], Size
- Offset
, " %a", ThumbMRegList ((OpCode
& 0xff) | ((OpCode
& BIT8
) == BIT8
? BIT15
: 0)));
364 AsciiSPrint (&Buf
[Offset
], Size
- Offset
, " %a", ThumbMRegList ((OpCode
& 0xff) | ((OpCode
& BIT8
) == BIT8
? BIT14
: 0)));
370 AsciiSPrint (&Buf
[Offset
], Size
- Offset
, " 0x%x", OpCode
& 0xff);
373 case CONDITIONAL_BRANCH
:
374 // A6.3.1 B<cond> <target_address>
375 // Patch in the condition code. A little hack but based on "%-6a"
376 Cond
= gCondition
[(OpCode
>> 8) & 0xf];
377 Buf
[Offset
-5] = *Cond
++;
378 Buf
[Offset
-4] = *Cond
;
379 AsciiSPrint (&Buf
[Offset
], Size
- Offset
, " 0x%04x", PC
+ 4 + SignExtend32 ((OpCode
& 0xff) << 1, BIT8
));
381 case UNCONDITIONAL_BRANCH_SHORT
:
382 // A6.3.2 B <target_address>
383 AsciiSPrint (&Buf
[Offset
], Size
- Offset
, " 0x%04x", PC
+ 4 + SignExtend32 ((OpCode
& 0x3ff) << 1, BIT11
));
386 case BRANCH_EXCHANGE
:
387 // A6.3.3 BX|BLX <Rm>
388 AsciiSPrint (&Buf
[Offset
], Size
- Offset
, " %a", gReg
[Rn
| (H2
? 8:0)]);
392 // A6.4.3 <Rd>, <Rn>, <Rm>
393 AsciiSPrint (&Buf
[Offset
], Size
- Offset
, " r%d, r%d, r%d", Rd
, Rn
, Rm
);
396 // A6.4.3 <Rd>, <Rn>, #3_bit_immed
397 AsciiSPrint (&Buf
[Offset
], Size
- Offset
, " r%d, r%d, 0x%x", Rd
, Rn
, Rm
);
400 // A6.4.3 <Rd>|<Rn>, #imm8
401 AsciiSPrint (&Buf
[Offset
], Size
- Offset
, " r%d, #0x%x", (OpCode
>> 8) & 7, OpCode
& 0xff);
404 // A6.4.3 <Rd>|<Rm>, #immed_5
405 AsciiSPrint (&Buf
[Offset
], Size
- Offset
, " r%d, r%d, 0x%x", Rn
, Rd
, (OpCode
>> 6) & 0x1f);
408 // A6.4.3 <Rd>|<Rm>, <Rm>|<Rs>
409 AsciiSPrint (&Buf
[Offset
], Size
- Offset
, " r%d, r%d", Rd
, Rn
);
411 case DATA_FORMAT6_SP
:
412 // A6.4.3 <Rd>, <reg>, #<8_Bit_immed>
413 AsciiSPrint (&Buf
[Offset
], Size
- Offset
, " r%d, sp, 0x%x", (OpCode
>> 8) & 7, (OpCode
& 0xff) << 2);
415 case DATA_FORMAT6_PC
:
416 // A6.4.3 <Rd>, <reg>, #<8_Bit_immed>
417 AsciiSPrint (&Buf
[Offset
], Size
- Offset
, " r%d, pc, 0x%x", (OpCode
>> 8) & 7, (OpCode
& 0xff) << 2);
420 // A6.4.3 SP, SP, #<7_Bit_immed>
421 AsciiSPrint (&Buf
[Offset
], Size
- Offset
, " sp, sp, 0x%x", (OpCode
& 0x7f)*4);
424 // A6.4.3 <Rd>|<Rn>, <Rm>
425 AsciiSPrint (&Buf
[Offset
], Size
- Offset
, " %a, %a", gReg
[Rd
| (H1
? 8:0)], gReg
[Rn
| (H2
? 8:0)]);
430 AsciiSPrint (&Buf
[Offset
], Size
- Offset
, "%a %a%a%a", imod
? "ID":"IE", ((OpCode
& BIT2
) == 0) ? "":"a", ((OpCode
& BIT1
) == 0) ? "":"i", ((OpCode
& BIT0
) == 0) ? "":"f");
435 AsciiSPrint (&Buf
[Offset
], Size
- Offset
, " %a", (OpCode
& BIT3
) == 0 ? "LE":"BE");
442 // Thumb2 are 32-bit instructions
444 for (Index
= 0; Index
< sizeof (gOpThumb2
)/sizeof (THUMB_INSTRUCTIONS
); Index
++) {
445 if ((OpCode32
& gOpThumb2
[Index
].Mask
) == gOpThumb2
[Index
].OpCode
) {
447 Offset
= AsciiSPrint (Buf
, Size
, "0x%04x %-6a", OpCode32
, gOpThumb2
[Index
].Start
);
449 Offset
= AsciiSPrint (Buf
, Size
, " %-6a", gOpThumb2
[Index
].Start
);
451 switch (gOpThumb2
[Index
].AddressMode
) {
453 Cond
= gCondition
[(OpCode32
>> 22) & 0xf];
454 Buf
[Offset
-5] = *Cond
++;
455 Buf
[Offset
-4] = *Cond
;
456 // S:J2:J1:imm6:imm11:0
457 Target
= ((OpCode32
<< 1) & 0xffe) + ((OpCode32
>> 4) & 0x3f000);
458 Target
|= ((OpCode32
& BIT11
) == BIT11
)? BIT19
: 0; // J2
459 Target
|= ((OpCode32
& BIT13
) == BIT13
)? BIT18
: 0; // J1
460 Target
|= ((OpCode32
& BIT26
) == BIT26
)? BIT20
: 0; // S
461 Target
= SignExtend32 (Target
, BIT20
);
462 AsciiSPrint (&Buf
[Offset
], Size
- Offset
, " 0x%08x", PC
+ 4 + Target
);
465 // S:I1:I2:imm10:imm11:0
466 Target
= ((OpCode32
<< 1) & 0xffe) + ((OpCode32
>> 4) & 0x3ff000);
467 S
= (OpCode32
& BIT26
) == BIT26
;
468 J1
= (OpCode32
& BIT13
) == BIT13
;
469 J2
= (OpCode32
& BIT11
) == BIT11
;
470 Target
|= (!(J2
^ S
) ? BIT22
: 0); // I2
471 Target
|= (!(J1
^ S
) ? BIT23
: 0); // I1
472 Target
|= (S
? BIT24
: 0); // S
473 Target
= SignExtend32 (Target
, BIT24
);
474 AsciiSPrint (&Buf
[Offset
], Size
- Offset
, " 0x%08x", PC
+ 4 + Target
);
478 // S:I1:I2:imm10:imm11:00
479 Target
= ((OpCode32
<< 2) & 0x1ffc) + ((OpCode32
>> 3) & 0x7fe000);
480 S
= (OpCode32
& BIT26
) == BIT26
;
481 J1
= (OpCode32
& BIT13
) == BIT13
;
482 J2
= (OpCode32
& BIT11
) == BIT11
;
483 Target
|= (!(J2
^ S
) ? BIT23
: 0); // I2
484 Target
|= (!(J1
^ S
) ? BIT24
: 0); // I1
485 Target
|= (S
? BIT25
: 0); // S
486 Target
= SignExtend32 (Target
, BIT25
);
487 AsciiSPrint (&Buf
[Offset
], Size
- Offset
, " 0x%08x", PC
+ 4 + Target
);
493 AsciiSPrint (Buf
, Size
, "0x%08x", OpCode32
);
499 DisassembleArmInstruction (
500 IN UINT32
**OpCodePtr
,
508 Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to
509 point to next instructin.
511 We cheat and only decode instructions that access
512 memory. If the instruction is not found we dump the instruction in hex.
514 @param OpCodePtrPtr Pointer to pointer of ARM Thumb instruction to disassemble.
515 @param Thumb TRUE for Thumb(2), FALSE for ARM instruction stream
516 @param Extended TRUE dump hex for instruction too.
517 @param Buf Buffer to sprintf disassembly into.
518 @param Size Size of Buf in bytes.
522 DisassembleInstruction (
523 IN UINT8
**OpCodePtr
,
531 DisassembleThumbInstruction ((UINT16
**)OpCodePtr
, Buf
, Size
, Extended
);
533 DisassembleArmInstruction ((UINT32
**)OpCodePtr
, Buf
, Size
, Extended
);