ArmPkg/Library/ArmGicArchSecLib/ArmGicArchLib.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2014, ARM Limited. All rights reserved.
   4 *
   5 *  SPDX-License-Identifier: BSD-2-Clause-Patent
   6 *
   7 **/
   8
   9 #include <Library/ArmLib.h>
  10 #include <Library/ArmGicLib.h>
  11
  12 ARM_GIC_ARCH_REVISION
  13 EFIAPI
  14 ArmGicGetSupportedArchRevision (
  15   VOID
  16   )
  17 {
  18   UINT32    IccSre;
  19
  20   // Ideally we would like to use the GICC IIDR Architecture version here, but
  21   // this does not seem to be very reliable as the implementation could easily
  22   // get it wrong. It is more reliable to check if the GICv3 System Register
  23   // feature is implemented on the CPU. This is also convenient as our GICv3
  24   // driver requires SRE. If only Memory mapped access is available we try to
  25   // drive the GIC as a v2.
  26   if (ArmHasGicSystemRegisters ()) {
  27     // Make sure System Register access is enabled (SRE). This depends on the
  28     // higher privilege level giving us permission, otherwise we will either
  29     // cause an exception here, or the write doesn't stick in which case we need
  30     // to fall back to the GICv2 MMIO interface.
  31     // Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started
  32     // at the same exception level.
  33     // It is the OS responsibility to set this bit.
  34     IccSre = ArmGicV3GetControlSystemRegisterEnable ();
  35     if (!(IccSre & ICC_SRE_EL2_SRE)) {
  36       ArmGicV3SetControlSystemRegisterEnable (IccSre | ICC_SRE_EL2_SRE);
  37       IccSre = ArmGicV3GetControlSystemRegisterEnable ();
  38     }
  39     if (IccSre & ICC_SRE_EL2_SRE) {
  40       return ARM_GIC_ARCH_REVISION_3;
  41     }
  42   }
  43
  44   return ARM_GIC_ARCH_REVISION_2;
  45 }