ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
   5   Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>
   6
   7   SPDX-License-Identifier: BSD-2-Clause-Patent
   8
   9 **/
  10
  11 #include <Base.h>
  12
  13 #include <Library/ArmLib.h>
  14 #include <Library/DebugLib.h>
  15
  16 #include <Chipset/AArch64.h>
  17
  18 #include "AArch64Lib.h"
  19 #include "ArmLibPrivate.h"
  20
  21 VOID
  22 AArch64DataCacheOperation (
  23   IN  AARCH64_CACHE_OPERATION  DataCacheOperation
  24   )
  25 {
  26   UINTN     SavedInterruptState;
  27
  28   SavedInterruptState = ArmGetInterruptState ();
  29   ArmDisableInterrupts();
  30
  31   AArch64AllDataCachesOperation (DataCacheOperation);
  32
  33   ArmDataSynchronizationBarrier ();
  34
  35   if (SavedInterruptState) {
  36     ArmEnableInterrupts ();
  37   }
  38 }
  39
  40 VOID
  41 EFIAPI
  42 ArmInvalidateDataCache (
  43   VOID
  44   )
  45 {
  46   ASSERT (!ArmMmuEnabled ());
  47
  48   ArmDataSynchronizationBarrier ();
  49   AArch64DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);
  50 }
  51
  52 VOID
  53 EFIAPI
  54 ArmCleanInvalidateDataCache (
  55   VOID
  56   )
  57 {
  58   ASSERT (!ArmMmuEnabled ());
  59
  60   ArmDataSynchronizationBarrier ();
  61   AArch64DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);
  62 }
  63
  64 VOID
  65 EFIAPI
  66 ArmCleanDataCache (
  67   VOID
  68   )
  69 {
  70   ASSERT (!ArmMmuEnabled ());
  71
  72   ArmDataSynchronizationBarrier ();
  73   AArch64DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
  74 }
  75
  76 /**
  77   Check whether the CPU supports the GIC system register interface (any version)
  78
  79   @return   Whether GIC System Register Interface is supported
  80
  81 **/
  82 BOOLEAN
  83 EFIAPI
  84 ArmHasGicSystemRegisters (
  85   VOID
  86   )
  87 {
  88   return ((ArmReadIdPfr0 () & AARCH64_PFR0_GIC) != 0);
  89 }