ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
   5
   6   This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #include <Uefi.h>
  17 #include <Chipset/AArch64.h>
  18 #include <Library/ArmLib.h>
  19 #include <Library/BaseLib.h>
  20 #include <Library/IoLib.h>
  21 #include "AArch64Lib.h"
  22 #include "ArmLibPrivate.h"
  23
  24 ARM_CACHE_TYPE
  25 EFIAPI
  26 ArmCacheType (
  27   VOID
  28   )
  29 {
  30   return ARM_CACHE_TYPE_WRITE_BACK;
  31 }
  32
  33 ARM_CACHE_ARCHITECTURE
  34 EFIAPI
  35 ArmCacheArchitecture (
  36   VOID
  37   )
  38 {
  39   UINT32 CLIDR = ReadCLIDR ();
  40
  41   return (ARM_CACHE_ARCHITECTURE)CLIDR; // BugBug Fix Me
  42 }
  43
  44 BOOLEAN
  45 EFIAPI
  46 ArmDataCachePresent (
  47   VOID
  48   )
  49 {
  50   UINT32 CLIDR = ReadCLIDR ();
  51
  52   if ((CLIDR & 0x2) == 0x2) {
  53     // Instruction cache exists
  54     return TRUE;
  55   }
  56   if ((CLIDR & 0x7) == 0x4) {
  57     // Unified cache
  58     return TRUE;
  59   }
  60
  61   return FALSE;
  62 }
  63
  64 UINTN
  65 EFIAPI
  66 ArmDataCacheSize (
  67   VOID
  68   )
  69 {
  70   UINT32 NumSets;
  71   UINT32 Associativity;
  72   UINT32 LineSize;
  73   UINT32 CCSIDR = ReadCCSIDR (0);
  74
  75   LineSize      = (1 << ((CCSIDR & 0x7) + 2));
  76   Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
  77   NumSets       = ((CCSIDR >> 13) & 0x7fff) + 1;
  78
  79   // LineSize is in words (4 byte chunks)
  80   return  NumSets * Associativity * LineSize * 4;
  81 }
  82
  83 UINTN
  84 EFIAPI
  85 ArmDataCacheAssociativity (
  86   VOID
  87   )
  88 {
  89   UINT32 CCSIDR = ReadCCSIDR (0);
  90
  91   return ((CCSIDR >> 3) & 0x3ff) + 1;
  92 }
  93
  94 UINTN
  95 ArmDataCacheSets (
  96   VOID
  97   )
  98 {
  99   UINT32 CCSIDR = ReadCCSIDR (0);
 100
 101   return ((CCSIDR >> 13) & 0x7fff) + 1;
 102 }
 103
 104 UINTN
 105 EFIAPI
 106 ArmDataCacheLineLength (
 107   VOID
 108   )
 109 {
 110   UINT32 CCSIDR = ReadCCSIDR (0) & 7;
 111
 112   // * 4 converts to bytes
 113   return (1 << (CCSIDR + 2)) * 4;
 114 }
 115
 116 BOOLEAN
 117 EFIAPI
 118 ArmInstructionCachePresent (
 119   VOID
 120   )
 121 {
 122   UINT32 CLIDR = ReadCLIDR ();
 123
 124   if ((CLIDR & 1) == 1) {
 125     // Instruction cache exists
 126     return TRUE;
 127   }
 128   if ((CLIDR & 0x7) == 0x4) {
 129     // Unified cache
 130     return TRUE;
 131   }
 132
 133   return FALSE;
 134 }
 135
 136 UINTN
 137 EFIAPI
 138 ArmInstructionCacheSize (
 139   VOID
 140   )
 141 {
 142   UINT32 NumSets;
 143   UINT32 Associativity;
 144   UINT32 LineSize;
 145   UINT32 CCSIDR = ReadCCSIDR (1);
 146
 147   LineSize      = (1 << ((CCSIDR & 0x7) + 2));
 148   Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
 149   NumSets       = ((CCSIDR >> 13) & 0x7fff) + 1;
 150
 151   // LineSize is in words (4 byte chunks)
 152   return  NumSets * Associativity * LineSize * 4;
 153 }
 154
 155 UINTN
 156 EFIAPI
 157 ArmInstructionCacheAssociativity (
 158   VOID
 159   )
 160 {
 161   UINT32 CCSIDR = ReadCCSIDR (1);
 162
 163   return ((CCSIDR >> 3) & 0x3ff) + 1;
 164 }
 165
 166 UINTN
 167 EFIAPI
 168 ArmInstructionCacheSets (
 169   VOID
 170   )
 171 {
 172   UINT32 CCSIDR = ReadCCSIDR (1);
 173
 174   return ((CCSIDR >> 13) & 0x7fff) + 1;
 175 }
 176
 177 UINTN
 178 EFIAPI
 179 ArmInstructionCacheLineLength (
 180   VOID
 181   )
 182 {
 183   UINT32 CCSIDR = ReadCCSIDR (1) & 7;
 184
 185   // * 4 converts to bytes
 186   return (1 << (CCSIDR + 2)) * 4;
 187 }
 188
 189
 190 VOID
 191 AArch64DataCacheOperation (
 192   IN  AARCH64_CACHE_OPERATION  DataCacheOperation
 193   )
 194 {
 195   UINTN     SavedInterruptState;
 196
 197   SavedInterruptState = ArmGetInterruptState ();
 198   ArmDisableInterrupts();
 199
 200   AArch64AllDataCachesOperation (DataCacheOperation);
 201
 202   ArmDrainWriteBuffer ();
 203
 204   if (SavedInterruptState) {
 205     ArmEnableInterrupts ();
 206   }
 207 }
 208
 209
 210 VOID
 211 AArch64PoUDataCacheOperation (
 212   IN  AARCH64_CACHE_OPERATION  DataCacheOperation
 213   )
 214 {
 215   UINTN     SavedInterruptState;
 216
 217   SavedInterruptState = ArmGetInterruptState ();
 218   ArmDisableInterrupts ();
 219
 220   AArch64PerformPoUDataCacheOperation (DataCacheOperation);
 221
 222   ArmDrainWriteBuffer ();
 223
 224   if (SavedInterruptState) {
 225     ArmEnableInterrupts ();
 226   }
 227 }
 228
 229 VOID
 230 EFIAPI
 231 ArmInvalidateDataCache (
 232   VOID
 233   )
 234 {
 235   AArch64DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);
 236 }
 237
 238 VOID
 239 EFIAPI
 240 ArmCleanInvalidateDataCache (
 241   VOID
 242   )
 243 {
 244   AArch64DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);
 245 }
 246
 247 VOID
 248 EFIAPI
 249 ArmCleanDataCache (
 250   VOID
 251   )
 252 {
 253   AArch64DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
 254 }
 255
 256 VOID
 257 EFIAPI
 258 ArmCleanDataCacheToPoU (
 259   VOID
 260   )
 261 {
 262   AArch64PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay);
 263 }