ArmPkg/Library/ArmLib/AArch64/AArch64Support.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
   5 #
   6 # This program and the accompanying materials
   7 # are licensed and made available under the terms and conditions of the BSD License
   8 # which accompanies this distribution.  The full text of the license may be found at
   9 # http://opensource.org/licenses/bsd-license.php
  10 #
  11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 #
  14 #------------------------------------------------------------------------------
  15
  16 #include <Chipset/AArch64.h>
  17 #include <AsmMacroIoLibV8.h>
  18
  19 .text
  20 .align 3
  21
  22 GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
  23 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
  24 GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
  25 GCC_ASM_EXPORT (ArmCleanDataCacheEntryToPoUByMVA)
  26 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
  27 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
  28 GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
  29 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)
  30 GCC_ASM_EXPORT (ArmEnableMmu)
  31 GCC_ASM_EXPORT (ArmDisableMmu)
  32 GCC_ASM_EXPORT (ArmDisableCachesAndMmu)
  33 GCC_ASM_EXPORT (ArmMmuEnabled)
  34 GCC_ASM_EXPORT (ArmEnableDataCache)
  35 GCC_ASM_EXPORT (ArmDisableDataCache)
  36 GCC_ASM_EXPORT (ArmEnableInstructionCache)
  37 GCC_ASM_EXPORT (ArmDisableInstructionCache)
  38 GCC_ASM_EXPORT (ArmDisableAlignmentCheck)
  39 GCC_ASM_EXPORT (ArmEnableAlignmentCheck)
  40 GCC_ASM_EXPORT (ArmEnableBranchPrediction)
  41 GCC_ASM_EXPORT (ArmDisableBranchPrediction)
  42 GCC_ASM_EXPORT (AArch64AllDataCachesOperation)
  43 GCC_ASM_EXPORT (ArmDataMemoryBarrier)
  44 GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)
  45 GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
  46 GCC_ASM_EXPORT (ArmWriteVBar)
  47 GCC_ASM_EXPORT (ArmReadVBar)
  48 GCC_ASM_EXPORT (ArmEnableVFP)
  49 GCC_ASM_EXPORT (ArmCallWFI)
  50 GCC_ASM_EXPORT (ArmReadMpidr)
  51 GCC_ASM_EXPORT (ArmReadTpidrurw)
  52 GCC_ASM_EXPORT (ArmWriteTpidrurw)
  53 GCC_ASM_EXPORT (ArmIsArchTimerImplemented)
  54 GCC_ASM_EXPORT (ArmReadIdPfr0)
  55 GCC_ASM_EXPORT (ArmReadIdPfr1)
  56 GCC_ASM_EXPORT (ArmWriteHcr)
  57 GCC_ASM_EXPORT (ArmReadHcr)
  58 GCC_ASM_EXPORT (ArmReadCurrentEL)
  59
  60 .set CTRL_M_BIT,      (1 << 0)
  61 .set CTRL_A_BIT,      (1 << 1)
  62 .set CTRL_C_BIT,      (1 << 2)
  63 .set CTRL_I_BIT,      (1 << 12)
  64 .set CTRL_V_BIT,      (1 << 12)
  65 .set CPACR_VFP_BITS,  (3 << 20)
  66
  67 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
  68   dc      ivac, x0    // Invalidate single data cache line
  69   ret
  70
  71
  72 ASM_PFX(ArmCleanDataCacheEntryByMVA):
  73   dc      cvac, x0    // Clean single data cache line
  74   ret
  75
  76
  77 ASM_PFX(ArmCleanDataCacheEntryToPoUByMVA):
  78   dc      cvau, x0    // Clean single data cache line to PoU
  79   ret
  80
  81
  82 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
  83   dc      civac, x0   // Clean and invalidate single data cache line
  84   ret
  85
  86
  87 ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
  88   dc      isw, x0     // Invalidate this line
  89   ret
  90
  91
  92 ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
  93   dc      cisw, x0    // Clean and Invalidate this line
  94   ret
  95
  96
  97 ASM_PFX(ArmCleanDataCacheEntryBySetWay):
  98   dc      csw, x0     // Clean this line
  99   ret
 100
 101
 102 ASM_PFX(ArmInvalidateInstructionCache):
 103   ic      iallu       // Invalidate entire instruction cache
 104   dsb     sy
 105   isb
 106   ret
 107
 108
 109 ASM_PFX(ArmEnableMmu):
 110    EL1_OR_EL2_OR_EL3(x1)
 111 1: mrs     x0, sctlr_el1       // Read System control register EL1
 112    b       4f
 113 2: mrs     x0, sctlr_el2       // Read System control register EL2
 114    b       4f
 115 3: mrs     x0, sctlr_el3       // Read System control register EL3
 116 4: orr     x0, x0, #CTRL_M_BIT // Set MMU enable bit
 117    EL1_OR_EL2_OR_EL3(x1)
 118 1: tlbi    vmalle1
 119    dsb     nsh
 120    isb
 121    msr     sctlr_el1, x0       // Write back
 122    b       4f
 123 2: tlbi    alle2
 124    dsb     nsh
 125    isb
 126    msr     sctlr_el2, x0       // Write back
 127    b       4f
 128 3: tlbi    alle3
 129    dsb     nsh
 130    isb
 131    msr     sctlr_el3, x0       // Write back
 132 4: isb
 133    ret
 134
 135
 136 ASM_PFX(ArmDisableMmu):
 137    EL1_OR_EL2_OR_EL3(x1)
 138 1: mrs     x0, sctlr_el1        // Read System Control Register EL1
 139    b       4f
 140 2: mrs     x0, sctlr_el2        // Read System Control Register EL2
 141    b       4f
 142 3: mrs     x0, sctlr_el3        // Read System Control Register EL3
 143 4: and     x0, x0, #~CTRL_M_BIT  // Clear MMU enable bit
 144    EL1_OR_EL2_OR_EL3(x1)
 145 1: msr     sctlr_el1, x0        // Write back
 146    tlbi    vmalle1
 147    b       4f
 148 2: msr     sctlr_el2, x0        // Write back
 149    tlbi    alle2
 150    b       4f
 151 3: msr     sctlr_el3, x0        // Write back
 152    tlbi    alle3
 153 4: dsb     sy
 154    isb
 155    ret
 156
 157
 158 ASM_PFX(ArmDisableCachesAndMmu):
 159    EL1_OR_EL2_OR_EL3(x1)
 160 1: mrs     x0, sctlr_el1        // Get control register EL1
 161    b       4f
 162 2: mrs     x0, sctlr_el2        // Get control register EL2
 163    b       4f
 164 3: mrs     x0, sctlr_el3        // Get control register EL3
 165 4: mov     x1, #~(CTRL_M_BIT | CTRL_C_BIT | CTRL_I_BIT)  // Disable MMU, D & I caches
 166    and     x0, x0, x1
 167    EL1_OR_EL2_OR_EL3(x1)
 168 1: msr     sctlr_el1, x0        // Write back control register
 169    b       4f
 170 2: msr     sctlr_el2, x0        // Write back control register
 171    b       4f
 172 3: msr     sctlr_el3, x0        // Write back control register
 173 4: dsb     sy
 174    isb
 175    ret
 176
 177
 178 ASM_PFX(ArmMmuEnabled):
 179    EL1_OR_EL2_OR_EL3(x1)
 180 1: mrs     x0, sctlr_el1        // Get control register EL1
 181    b       4f
 182 2: mrs     x0, sctlr_el2        // Get control register EL2
 183    b       4f
 184 3: mrs     x0, sctlr_el3        // Get control register EL3
 185 4: and     x0, x0, #CTRL_M_BIT
 186    ret
 187
 188
 189 ASM_PFX(ArmEnableDataCache):
 190    EL1_OR_EL2_OR_EL3(x1)
 191 1: mrs     x0, sctlr_el1        // Get control register EL1
 192    b       4f
 193 2: mrs     x0, sctlr_el2        // Get control register EL2
 194    b       4f
 195 3: mrs     x0, sctlr_el3        // Get control register EL3
 196 4: orr     x0, x0, #CTRL_C_BIT  // Set C bit
 197    EL1_OR_EL2_OR_EL3(x1)
 198 1: msr     sctlr_el1, x0        // Write back control register
 199    b       4f
 200 2: msr     sctlr_el2, x0        // Write back control register
 201    b       4f
 202 3: msr     sctlr_el3, x0        // Write back control register
 203 4: dsb     sy
 204    isb
 205    ret
 206
 207
 208 ASM_PFX(ArmDisableDataCache):
 209    EL1_OR_EL2_OR_EL3(x1)
 210 1: mrs     x0, sctlr_el1        // Get control register EL1
 211    b       4f
 212 2: mrs     x0, sctlr_el2        // Get control register EL2
 213    b       4f
 214 3: mrs     x0, sctlr_el3        // Get control register EL3
 215 4: and     x0, x0, #~CTRL_C_BIT  // Clear C bit
 216    EL1_OR_EL2_OR_EL3(x1)
 217 1: msr     sctlr_el1, x0        // Write back control register
 218    b       4f
 219 2: msr     sctlr_el2, x0        // Write back control register
 220    b       4f
 221 3: msr     sctlr_el3, x0        // Write back control register
 222 4: dsb     sy
 223    isb
 224    ret
 225
 226
 227 ASM_PFX(ArmEnableInstructionCache):
 228    EL1_OR_EL2_OR_EL3(x1)
 229 1: mrs     x0, sctlr_el1        // Get control register EL1
 230    b       4f
 231 2: mrs     x0, sctlr_el2        // Get control register EL2
 232    b       4f
 233 3: mrs     x0, sctlr_el3        // Get control register EL3
 234 4: orr     x0, x0, #CTRL_I_BIT  // Set I bit
 235    EL1_OR_EL2_OR_EL3(x1)
 236 1: msr     sctlr_el1, x0        // Write back control register
 237    b       4f
 238 2: msr     sctlr_el2, x0        // Write back control register
 239    b       4f
 240 3: msr     sctlr_el3, x0        // Write back control register
 241 4: dsb     sy
 242    isb
 243    ret
 244
 245
 246 ASM_PFX(ArmDisableInstructionCache):
 247    EL1_OR_EL2_OR_EL3(x1)
 248 1: mrs     x0, sctlr_el1        // Get control register EL1
 249    b       4f
 250 2: mrs     x0, sctlr_el2        // Get control register EL2
 251    b       4f
 252 3: mrs     x0, sctlr_el3        // Get control register EL3
 253 4: and     x0, x0, #~CTRL_I_BIT  // Clear I bit
 254    EL1_OR_EL2_OR_EL3(x1)
 255 1: msr     sctlr_el1, x0        // Write back control register
 256    b       4f
 257 2: msr     sctlr_el2, x0        // Write back control register
 258    b       4f
 259 3: msr     sctlr_el3, x0        // Write back control register
 260 4: dsb     sy
 261    isb
 262    ret
 263
 264
 265 ASM_PFX(ArmEnableAlignmentCheck):
 266    EL1_OR_EL2(x1)
 267 1: mrs     x0, sctlr_el1        // Get control register EL1
 268    b       3f
 269 2: mrs     x0, sctlr_el2        // Get control register EL2
 270 3: orr     x0, x0, #CTRL_A_BIT  // Set A (alignment check) bit
 271    EL1_OR_EL2(x1)
 272 1: msr     sctlr_el1, x0        // Write back control register
 273    b       3f
 274 2: msr     sctlr_el2, x0        // Write back control register
 275 3: dsb     sy
 276    isb
 277    ret
 278
 279
 280 ASM_PFX(ArmDisableAlignmentCheck):
 281    EL1_OR_EL2_OR_EL3(x1)
 282 1: mrs     x0, sctlr_el1        // Get control register EL1
 283    b       4f
 284 2: mrs     x0, sctlr_el2        // Get control register EL2
 285    b       4f
 286 3: mrs     x0, sctlr_el3        // Get control register EL3
 287 4: and     x0, x0, #~CTRL_A_BIT  // Clear A (alignment check) bit
 288    EL1_OR_EL2_OR_EL3(x1)
 289 1: msr     sctlr_el1, x0        // Write back control register
 290    b       4f
 291 2: msr     sctlr_el2, x0        // Write back control register
 292    b       4f
 293 3: msr     sctlr_el3, x0        // Write back control register
 294 4: dsb     sy
 295    isb
 296    ret
 297
 298
 299 // Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now
 300 ASM_PFX(ArmEnableBranchPrediction):
 301   ret
 302
 303
 304 // Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now.
 305 ASM_PFX(ArmDisableBranchPrediction):
 306   ret
 307
 308
 309 ASM_PFX(AArch64AllDataCachesOperation):
 310 // We can use regs 0-7 and 9-15 without having to save/restore.
 311 // Save our link register on the stack. - The stack must always be quad-word aligned
 312   str   x30, [sp, #-16]!
 313   mov   x1, x0                  // Save Function call in x1
 314   mrs   x6, clidr_el1           // Read EL1 CLIDR
 315   and   x3, x6, #0x7000000      // Mask out all but Level of Coherency (LoC)
 316   lsr   x3, x3, #23             // Left align cache level value - the level is shifted by 1 to the
 317                                 // right to ease the access to CSSELR and the Set/Way operation.
 318   cbz   x3, L_Finished          // No need to clean if LoC is 0
 319   mov   x10, #0                 // Start clean at cache level 0
 320
 321 Loop1:
 322   add   x2, x10, x10, lsr #1    // Work out 3x cachelevel for cache info
 323   lsr   x12, x6, x2             // bottom 3 bits are the Cache type for this level
 324   and   x12, x12, #7            // get those 3 bits alone
 325   cmp   x12, #2                 // what cache at this level?
 326   b.lt  L_Skip                  // no cache or only instruction cache at this level
 327   msr   csselr_el1, x10         // write the Cache Size selection register with current level (CSSELR)
 328   isb                           // isb to sync the change to the CacheSizeID reg
 329   mrs   x12, ccsidr_el1         // reads current Cache Size ID register (CCSIDR)
 330   and   x2, x12, #0x7           // extract the line length field
 331   add   x2, x2, #4              // add 4 for the line length offset (log2 16 bytes)
 332   mov   x4, #0x400
 333   sub   x4, x4, #1
 334   and   x4, x4, x12, lsr #3     // x4 is the max number on the way size (right aligned)
 335   clz   w5, w4                  // w5 is the bit position of the way size increment
 336   mov   x7, #0x00008000
 337   sub   x7, x7, #1
 338   and   x7, x7, x12, lsr #13    // x7 is the max number of the index size (right aligned)
 339
 340 Loop2:
 341   mov   x9, x4                  // x9 working copy of the max way size (right aligned)
 342
 343 Loop3:
 344   lsl   x11, x9, x5
 345   orr   x0, x10, x11            // factor in the way number and cache number
 346   lsl   x11, x7, x2
 347   orr   x0, x0, x11             // factor in the index number
 348
 349   blr   x1                      // Goto requested cache operation
 350
 351   subs  x9, x9, #1              // decrement the way number
 352   b.ge  Loop3
 353   subs  x7, x7, #1              // decrement the index
 354   b.ge  Loop2
 355 L_Skip:
 356   add   x10, x10, #2            // increment the cache number
 357   cmp   x3, x10
 358   b.gt  Loop1
 359
 360 L_Finished:
 361   dsb   sy
 362   isb
 363   ldr   x30, [sp], #0x10
 364   ret
 365
 366
 367 ASM_PFX(ArmDataMemoryBarrier):
 368   dmb   sy
 369   ret
 370
 371
 372 ASM_PFX(ArmDataSynchronizationBarrier):
 373   dsb   sy
 374   ret
 375
 376
 377 ASM_PFX(ArmInstructionSynchronizationBarrier):
 378   isb
 379   ret
 380
 381
 382 ASM_PFX(ArmWriteVBar):
 383    EL1_OR_EL2_OR_EL3(x1)
 384 1: msr   vbar_el1, x0            // Set the Address of the EL1 Vector Table in the VBAR register
 385    b     4f
 386 2: msr   vbar_el2, x0            // Set the Address of the EL2 Vector Table in the VBAR register
 387    b     4f
 388 3: msr   vbar_el3, x0            // Set the Address of the EL3 Vector Table in the VBAR register
 389 4: isb
 390    ret
 391
 392 ASM_PFX(ArmReadVBar):
 393    EL1_OR_EL2_OR_EL3(x1)
 394 1: mrs   x0, vbar_el1            // Set the Address of the EL1 Vector Table in the VBAR register
 395    ret
 396 2: mrs   x0, vbar_el2            // Set the Address of the EL2 Vector Table in the VBAR register
 397    ret
 398 3: mrs   x0, vbar_el3            // Set the Address of the EL3 Vector Table in the VBAR register
 399    ret
 400
 401
 402 ASM_PFX(ArmEnableVFP):
 403   // Check whether floating-point is implemented in the processor.
 404   mov   x1, x30                 // Save LR
 405   bl    ArmReadIdPfr0           // Read EL1 Processor Feature Register (PFR0)
 406   mov   x30, x1                 // Restore LR
 407   ands  x0, x0, #AARCH64_PFR0_FP// Extract bits indicating VFP implementation
 408   cmp   x0, #0                  // VFP is implemented if '0'.
 409   b.ne  4f                      // Exit if VFP not implemented.
 410   // FVP is implemented.
 411   // Make sure VFP exceptions are not trapped (to any exception level).
 412   mrs   x0, cpacr_el1           // Read EL1 Coprocessor Access Control Register (CPACR)
 413   orr   x0, x0, #CPACR_VFP_BITS // Disable FVP traps to EL1
 414   msr   cpacr_el1, x0           // Write back EL1 Coprocessor Access Control Register (CPACR)
 415   mov   x1, #AARCH64_CPTR_TFP   // TFP Bit for trapping VFP Exceptions
 416   EL1_OR_EL2_OR_EL3(x2)
 417 1:ret                           // Not configurable in EL1
 418 2:mrs   x0, cptr_el2            // Disable VFP traps to EL2
 419   bic   x0, x0, x1
 420   msr   cptr_el2, x0
 421   ret
 422 3:mrs   x0, cptr_el3            // Disable VFP traps to EL3
 423   bic   x0, x0, x1
 424   msr   cptr_el3, x0
 425 4:ret
 426
 427
 428 ASM_PFX(ArmCallWFI):
 429   wfi
 430   ret
 431
 432
 433 ASM_PFX(ArmReadMpidr):
 434   mrs   x0, mpidr_el1           // read EL1 MPIDR
 435   ret
 436
 437
 438 // Keep old function names for C compatibilty for now. Change later?
 439 ASM_PFX(ArmReadTpidrurw):
 440   mrs   x0, tpidr_el0           // read tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)
 441   ret
 442
 443
 444 // Keep old function names for C compatibilty for now. Change later?
 445 ASM_PFX(ArmWriteTpidrurw):
 446   msr   tpidr_el0, x0           // write tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)
 447   ret
 448
 449
 450 // Arch timers are mandatory on AArch64
 451 ASM_PFX(ArmIsArchTimerImplemented):
 452   mov   x0, #1
 453   ret
 454
 455
 456 ASM_PFX(ArmReadIdPfr0):
 457   mrs   x0, id_aa64pfr0_el1   // Read ID_AA64PFR0 Register
 458   ret
 459
 460
 461 // Q: id_aa64pfr1_el1 not defined yet. What does this funtion want to access?
 462 // A: used to setup arch timer. Check if we have security extensions, permissions to set stuff.
 463 //    See: ArmPkg/Library/ArmArchTimerLib/AArch64/ArmArchTimerLib.c
 464 //    Not defined yet, but stick in here for now, should read all zeros.
 465 ASM_PFX(ArmReadIdPfr1):
 466   mrs   x0, id_aa64pfr1_el1   // Read ID_PFR1 Register
 467   ret
 468
 469 // VOID ArmWriteHcr(UINTN Hcr)
 470 ASM_PFX(ArmWriteHcr):
 471   msr   hcr_el2, x0        // Write the passed HCR value
 472   ret
 473
 474 // UINTN ArmReadHcr(VOID)
 475 ASM_PFX(ArmReadHcr):
 476   mrs   x0, hcr_el2
 477   ret
 478
 479 // UINTN ArmReadCurrentEL(VOID)
 480 ASM_PFX(ArmReadCurrentEL):
 481   mrs   x0, CurrentEL
 482   ret
 483
 484 ASM_FUNCTION_REMOVE_IF_UNREFERENCED