ArmPkg/Library/ArmLib/AArch64/AArch64Support.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011 - 2017, ARM Limited. All rights reserved.
   5 # Copyright (c) 2016, Linaro Limited. All rights reserved.
   6 #
   7 # This program and the accompanying materials
   8 # are licensed and made available under the terms and conditions of the BSD License
   9 # which accompanies this distribution.  The full text of the license may be found at
  10 # http://opensource.org/licenses/bsd-license.php
  11 #
  12 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14 #
  15 #------------------------------------------------------------------------------
  16
  17 #include <Chipset/AArch64.h>
  18 #include <AsmMacroIoLibV8.h>
  19
  20 .set CTRL_M_BIT,      (1 << 0)
  21 .set CTRL_A_BIT,      (1 << 1)
  22 .set CTRL_C_BIT,      (1 << 2)
  23 .set CTRL_SA_BIT,     (1 << 3)
  24 .set CTRL_I_BIT,      (1 << 12)
  25 .set CTRL_V_BIT,      (1 << 12)
  26 .set CPACR_VFP_BITS,  (3 << 20)
  27
  28 ASM_FUNC(ArmInvalidateDataCacheEntryByMVA)
  29   dc      ivac, x0    // Invalidate single data cache line
  30   ret
  31
  32
  33 ASM_FUNC(ArmCleanDataCacheEntryByMVA)
  34   dc      cvac, x0    // Clean single data cache line
  35   ret
  36
  37
  38 ASM_FUNC(ArmCleanDataCacheEntryToPoUByMVA)
  39   dc      cvau, x0    // Clean single data cache line to PoU
  40   ret
  41
  42 ASM_FUNC(ArmInvalidateInstructionCacheEntryToPoUByMVA)
  43   ic      ivau, x0    // Invalidate single instruction cache line to PoU
  44   ret
  45
  46
  47 ASM_FUNC(ArmCleanInvalidateDataCacheEntryByMVA)
  48   dc      civac, x0   // Clean and invalidate single data cache line
  49   ret
  50
  51
  52 ASM_FUNC(ArmInvalidateDataCacheEntryBySetWay)
  53   dc      isw, x0     // Invalidate this line
  54   ret
  55
  56
  57 ASM_FUNC(ArmCleanInvalidateDataCacheEntryBySetWay)
  58   dc      cisw, x0    // Clean and Invalidate this line
  59   ret
  60
  61
  62 ASM_FUNC(ArmCleanDataCacheEntryBySetWay)
  63   dc      csw, x0     // Clean this line
  64   ret
  65
  66
  67 ASM_FUNC(ArmInvalidateInstructionCache)
  68   ic      iallu       // Invalidate entire instruction cache
  69   dsb     sy
  70   isb
  71   ret
  72
  73
  74 ASM_FUNC(ArmEnableMmu)
  75    EL1_OR_EL2_OR_EL3(x1)
  76 1: mrs     x0, sctlr_el1       // Read System control register EL1
  77    b       4f
  78 2: mrs     x0, sctlr_el2       // Read System control register EL2
  79    b       4f
  80 3: mrs     x0, sctlr_el3       // Read System control register EL3
  81 4: orr     x0, x0, #CTRL_M_BIT // Set MMU enable bit
  82    EL1_OR_EL2_OR_EL3(x1)
  83 1: tlbi    vmalle1
  84    dsb     nsh
  85    isb
  86    msr     sctlr_el1, x0       // Write back
  87    b       4f
  88 2: tlbi    alle2
  89    dsb     nsh
  90    isb
  91    msr     sctlr_el2, x0       // Write back
  92    b       4f
  93 3: tlbi    alle3
  94    dsb     nsh
  95    isb
  96    msr     sctlr_el3, x0       // Write back
  97 4: isb
  98    ret
  99
 100
 101 ASM_FUNC(ArmDisableMmu)
 102    EL1_OR_EL2_OR_EL3(x1)
 103 1: mrs     x0, sctlr_el1        // Read System Control Register EL1
 104    b       4f
 105 2: mrs     x0, sctlr_el2        // Read System Control Register EL2
 106    b       4f
 107 3: mrs     x0, sctlr_el3        // Read System Control Register EL3
 108 4: and     x0, x0, #~CTRL_M_BIT  // Clear MMU enable bit
 109    EL1_OR_EL2_OR_EL3(x1)
 110 1: msr     sctlr_el1, x0        // Write back
 111    tlbi    vmalle1
 112    b       4f
 113 2: msr     sctlr_el2, x0        // Write back
 114    tlbi    alle2
 115    b       4f
 116 3: msr     sctlr_el3, x0        // Write back
 117    tlbi    alle3
 118 4: dsb     sy
 119    isb
 120    ret
 121
 122
 123 ASM_FUNC(ArmDisableCachesAndMmu)
 124    EL1_OR_EL2_OR_EL3(x1)
 125 1: mrs     x0, sctlr_el1        // Get control register EL1
 126    b       4f
 127 2: mrs     x0, sctlr_el2        // Get control register EL2
 128    b       4f
 129 3: mrs     x0, sctlr_el3        // Get control register EL3
 130 4: mov     x1, #~(CTRL_M_BIT | CTRL_C_BIT | CTRL_I_BIT)  // Disable MMU, D & I caches
 131    and     x0, x0, x1
 132    EL1_OR_EL2_OR_EL3(x1)
 133 1: msr     sctlr_el1, x0        // Write back control register
 134    b       4f
 135 2: msr     sctlr_el2, x0        // Write back control register
 136    b       4f
 137 3: msr     sctlr_el3, x0        // Write back control register
 138 4: dsb     sy
 139    isb
 140    ret
 141
 142
 143 ASM_FUNC(ArmMmuEnabled)
 144    EL1_OR_EL2_OR_EL3(x1)
 145 1: mrs     x0, sctlr_el1        // Get control register EL1
 146    b       4f
 147 2: mrs     x0, sctlr_el2        // Get control register EL2
 148    b       4f
 149 3: mrs     x0, sctlr_el3        // Get control register EL3
 150 4: and     x0, x0, #CTRL_M_BIT
 151    ret
 152
 153
 154 ASM_FUNC(ArmEnableDataCache)
 155    EL1_OR_EL2_OR_EL3(x1)
 156 1: mrs     x0, sctlr_el1        // Get control register EL1
 157    b       4f
 158 2: mrs     x0, sctlr_el2        // Get control register EL2
 159    b       4f
 160 3: mrs     x0, sctlr_el3        // Get control register EL3
 161 4: orr     x0, x0, #CTRL_C_BIT  // Set C bit
 162    EL1_OR_EL2_OR_EL3(x1)
 163 1: msr     sctlr_el1, x0        // Write back control register
 164    b       4f
 165 2: msr     sctlr_el2, x0        // Write back control register
 166    b       4f
 167 3: msr     sctlr_el3, x0        // Write back control register
 168 4: dsb     sy
 169    isb
 170    ret
 171
 172
 173 ASM_FUNC(ArmDisableDataCache)
 174    EL1_OR_EL2_OR_EL3(x1)
 175 1: mrs     x0, sctlr_el1        // Get control register EL1
 176    b       4f
 177 2: mrs     x0, sctlr_el2        // Get control register EL2
 178    b       4f
 179 3: mrs     x0, sctlr_el3        // Get control register EL3
 180 4: and     x0, x0, #~CTRL_C_BIT  // Clear C bit
 181    EL1_OR_EL2_OR_EL3(x1)
 182 1: msr     sctlr_el1, x0        // Write back control register
 183    b       4f
 184 2: msr     sctlr_el2, x0        // Write back control register
 185    b       4f
 186 3: msr     sctlr_el3, x0        // Write back control register
 187 4: dsb     sy
 188    isb
 189    ret
 190
 191
 192 ASM_FUNC(ArmEnableInstructionCache)
 193    EL1_OR_EL2_OR_EL3(x1)
 194 1: mrs     x0, sctlr_el1        // Get control register EL1
 195    b       4f
 196 2: mrs     x0, sctlr_el2        // Get control register EL2
 197    b       4f
 198 3: mrs     x0, sctlr_el3        // Get control register EL3
 199 4: orr     x0, x0, #CTRL_I_BIT  // Set I bit
 200    EL1_OR_EL2_OR_EL3(x1)
 201 1: msr     sctlr_el1, x0        // Write back control register
 202    b       4f
 203 2: msr     sctlr_el2, x0        // Write back control register
 204    b       4f
 205 3: msr     sctlr_el3, x0        // Write back control register
 206 4: dsb     sy
 207    isb
 208    ret
 209
 210
 211 ASM_FUNC(ArmDisableInstructionCache)
 212    EL1_OR_EL2_OR_EL3(x1)
 213 1: mrs     x0, sctlr_el1        // Get control register EL1
 214    b       4f
 215 2: mrs     x0, sctlr_el2        // Get control register EL2
 216    b       4f
 217 3: mrs     x0, sctlr_el3        // Get control register EL3
 218 4: and     x0, x0, #~CTRL_I_BIT  // Clear I bit
 219    EL1_OR_EL2_OR_EL3(x1)
 220 1: msr     sctlr_el1, x0        // Write back control register
 221    b       4f
 222 2: msr     sctlr_el2, x0        // Write back control register
 223    b       4f
 224 3: msr     sctlr_el3, x0        // Write back control register
 225 4: dsb     sy
 226    isb
 227    ret
 228
 229
 230 ASM_FUNC(ArmEnableAlignmentCheck)
 231    EL1_OR_EL2(x1)
 232 1: mrs     x0, sctlr_el1        // Get control register EL1
 233    b       3f
 234 2: mrs     x0, sctlr_el2        // Get control register EL2
 235 3: orr     x0, x0, #CTRL_A_BIT  // Set A (alignment check) bit
 236    EL1_OR_EL2(x1)
 237 1: msr     sctlr_el1, x0        // Write back control register
 238    b       3f
 239 2: msr     sctlr_el2, x0        // Write back control register
 240 3: dsb     sy
 241    isb
 242    ret
 243
 244
 245 ASM_FUNC(ArmDisableAlignmentCheck)
 246    EL1_OR_EL2_OR_EL3(x1)
 247 1: mrs     x0, sctlr_el1        // Get control register EL1
 248    b       4f
 249 2: mrs     x0, sctlr_el2        // Get control register EL2
 250    b       4f
 251 3: mrs     x0, sctlr_el3        // Get control register EL3
 252 4: and     x0, x0, #~CTRL_A_BIT  // Clear A (alignment check) bit
 253    EL1_OR_EL2_OR_EL3(x1)
 254 1: msr     sctlr_el1, x0        // Write back control register
 255    b       4f
 256 2: msr     sctlr_el2, x0        // Write back control register
 257    b       4f
 258 3: msr     sctlr_el3, x0        // Write back control register
 259 4: dsb     sy
 260    isb
 261    ret
 262
 263 ASM_FUNC(ArmEnableStackAlignmentCheck)
 264    EL1_OR_EL2(x1)
 265 1: mrs     x0, sctlr_el1        // Get control register EL1
 266    b       3f
 267 2: mrs     x0, sctlr_el2        // Get control register EL2
 268 3: orr     x0, x0, #CTRL_SA_BIT // Set SA (stack alignment check) bit
 269    EL1_OR_EL2(x1)
 270 1: msr     sctlr_el1, x0        // Write back control register
 271    b       3f
 272 2: msr     sctlr_el2, x0        // Write back control register
 273 3: dsb     sy
 274    isb
 275    ret
 276
 277
 278 ASM_FUNC(ArmDisableStackAlignmentCheck)
 279    EL1_OR_EL2_OR_EL3(x1)
 280 1: mrs     x0, sctlr_el1        // Get control register EL1
 281    b       4f
 282 2: mrs     x0, sctlr_el2        // Get control register EL2
 283    b       4f
 284 3: mrs     x0, sctlr_el3        // Get control register EL3
 285 4: bic     x0, x0, #CTRL_SA_BIT // Clear SA (stack alignment check) bit
 286    EL1_OR_EL2_OR_EL3(x1)
 287 1: msr     sctlr_el1, x0        // Write back control register
 288    b       4f
 289 2: msr     sctlr_el2, x0        // Write back control register
 290    b       4f
 291 3: msr     sctlr_el3, x0        // Write back control register
 292 4: dsb     sy
 293    isb
 294    ret
 295
 296
 297 // Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now
 298 ASM_FUNC(ArmEnableBranchPrediction)
 299   ret
 300
 301
 302 // Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now.
 303 ASM_FUNC(ArmDisableBranchPrediction)
 304   ret
 305
 306
 307 ASM_FUNC(AArch64AllDataCachesOperation)
 308 // We can use regs 0-7 and 9-15 without having to save/restore.
 309 // Save our link register on the stack. - The stack must always be quad-word aligned
 310   stp   x29, x30, [sp, #-16]!
 311   mov   x29, sp
 312   mov   x1, x0                  // Save Function call in x1
 313   mrs   x6, clidr_el1           // Read EL1 CLIDR
 314   and   x3, x6, #0x7000000      // Mask out all but Level of Coherency (LoC)
 315   lsr   x3, x3, #23             // Left align cache level value - the level is shifted by 1 to the
 316                                 // right to ease the access to CSSELR and the Set/Way operation.
 317   cbz   x3, L_Finished          // No need to clean if LoC is 0
 318   mov   x10, #0                 // Start clean at cache level 0
 319
 320 Loop1:
 321   add   x2, x10, x10, lsr #1    // Work out 3x cachelevel for cache info
 322   lsr   x12, x6, x2             // bottom 3 bits are the Cache type for this level
 323   and   x12, x12, #7            // get those 3 bits alone
 324   cmp   x12, #2                 // what cache at this level?
 325   b.lt  L_Skip                  // no cache or only instruction cache at this level
 326   msr   csselr_el1, x10         // write the Cache Size selection register with current level (CSSELR)
 327   isb                           // isb to sync the change to the CacheSizeID reg
 328   mrs   x12, ccsidr_el1         // reads current Cache Size ID register (CCSIDR)
 329   and   x2, x12, #0x7           // extract the line length field
 330   add   x2, x2, #4              // add 4 for the line length offset (log2 16 bytes)
 331   mov   x4, #0x400
 332   sub   x4, x4, #1
 333   and   x4, x4, x12, lsr #3     // x4 is the max number on the way size (right aligned)
 334   clz   w5, w4                  // w5 is the bit position of the way size increment
 335   mov   x7, #0x00008000
 336   sub   x7, x7, #1
 337   and   x7, x7, x12, lsr #13    // x7 is the max number of the index size (right aligned)
 338
 339 Loop2:
 340   mov   x9, x4                  // x9 working copy of the max way size (right aligned)
 341
 342 Loop3:
 343   lsl   x11, x9, x5
 344   orr   x0, x10, x11            // factor in the way number and cache number
 345   lsl   x11, x7, x2
 346   orr   x0, x0, x11             // factor in the index number
 347
 348   blr   x1                      // Goto requested cache operation
 349
 350   subs  x9, x9, #1              // decrement the way number
 351   b.ge  Loop3
 352   subs  x7, x7, #1              // decrement the index
 353   b.ge  Loop2
 354 L_Skip:
 355   add   x10, x10, #2            // increment the cache number
 356   cmp   x3, x10
 357   b.gt  Loop1
 358
 359 L_Finished:
 360   dsb   sy
 361   isb
 362   ldp   x29, x30, [sp], #0x10
 363   ret
 364
 365
 366 ASM_FUNC(ArmDataMemoryBarrier)
 367   dmb   sy
 368   ret
 369
 370
 371 ASM_FUNC(ArmDataSynchronizationBarrier)
 372   dsb   sy
 373   ret
 374
 375
 376 ASM_FUNC(ArmInstructionSynchronizationBarrier)
 377   isb
 378   ret
 379
 380
 381 ASM_FUNC(ArmWriteVBar)
 382    EL1_OR_EL2_OR_EL3(x1)
 383 1: msr   vbar_el1, x0            // Set the Address of the EL1 Vector Table in the VBAR register
 384    b     4f
 385 2: msr   vbar_el2, x0            // Set the Address of the EL2 Vector Table in the VBAR register
 386    b     4f
 387 3: msr   vbar_el3, x0            // Set the Address of the EL3 Vector Table in the VBAR register
 388 4: isb
 389    ret
 390
 391 ASM_FUNC(ArmReadVBar)
 392    EL1_OR_EL2_OR_EL3(x1)
 393 1: mrs   x0, vbar_el1            // Set the Address of the EL1 Vector Table in the VBAR register
 394    ret
 395 2: mrs   x0, vbar_el2            // Set the Address of the EL2 Vector Table in the VBAR register
 396    ret
 397 3: mrs   x0, vbar_el3            // Set the Address of the EL3 Vector Table in the VBAR register
 398    ret
 399
 400
 401 ASM_FUNC(ArmEnableVFP)
 402   // Check whether floating-point is implemented in the processor.
 403   mov   x1, x30                 // Save LR
 404   bl    ArmReadIdPfr0           // Read EL1 Processor Feature Register (PFR0)
 405   mov   x30, x1                 // Restore LR
 406   ubfx  x0, x0, #16, #4         // Extract the FP bits 16:19
 407   cmp   x0, #0xF                // Check if FP bits are '1111b',
 408                                 // i.e. Floating Point not implemented
 409   b.eq  4f                      // Exit when VFP is not implemented.
 410
 411   // FVP is implemented.
 412   // Make sure VFP exceptions are not trapped (to any exception level).
 413   mrs   x0, cpacr_el1           // Read EL1 Coprocessor Access Control Register (CPACR)
 414   orr   x0, x0, #CPACR_VFP_BITS // Disable FVP traps to EL1
 415   msr   cpacr_el1, x0           // Write back EL1 Coprocessor Access Control Register (CPACR)
 416   mov   x1, #AARCH64_CPTR_TFP   // TFP Bit for trapping VFP Exceptions
 417   EL1_OR_EL2_OR_EL3(x2)
 418 1:ret                           // Not configurable in EL1
 419 2:mrs   x0, cptr_el2            // Disable VFP traps to EL2
 420   bic   x0, x0, x1
 421   msr   cptr_el2, x0
 422   ret
 423 3:mrs   x0, cptr_el3            // Disable VFP traps to EL3
 424   bic   x0, x0, x1
 425   msr   cptr_el3, x0
 426 4:ret
 427
 428
 429 ASM_FUNC(ArmCallWFI)
 430   wfi
 431   ret
 432
 433
 434 ASM_FUNC(ArmReadMpidr)
 435   mrs   x0, mpidr_el1           // read EL1 MPIDR
 436   ret
 437
 438
 439 // Keep old function names for C compatibilty for now. Change later?
 440 ASM_FUNC(ArmReadTpidrurw)
 441   mrs   x0, tpidr_el0           // read tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)
 442   ret
 443
 444
 445 // Keep old function names for C compatibilty for now. Change later?
 446 ASM_FUNC(ArmWriteTpidrurw)
 447   msr   tpidr_el0, x0           // write tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)
 448   ret
 449
 450
 451 // Arch timers are mandatory on AArch64
 452 ASM_FUNC(ArmIsArchTimerImplemented)
 453   mov   x0, #1
 454   ret
 455
 456
 457 ASM_FUNC(ArmReadIdPfr0)
 458   mrs   x0, id_aa64pfr0_el1   // Read ID_AA64PFR0 Register
 459   ret
 460
 461
 462 // Q: id_aa64pfr1_el1 not defined yet. What does this funtion want to access?
 463 // A: used to setup arch timer. Check if we have security extensions, permissions to set stuff.
 464 //    See: ArmPkg/Library/ArmArchTimerLib/AArch64/ArmArchTimerLib.c
 465 //    Not defined yet, but stick in here for now, should read all zeros.
 466 ASM_FUNC(ArmReadIdPfr1)
 467   mrs   x0, id_aa64pfr1_el1   // Read ID_PFR1 Register
 468   ret
 469
 470 // VOID ArmWriteHcr(UINTN Hcr)
 471 ASM_FUNC(ArmWriteHcr)
 472   msr   hcr_el2, x0        // Write the passed HCR value
 473   ret
 474
 475 // UINTN ArmReadHcr(VOID)
 476 ASM_FUNC(ArmReadHcr)
 477   mrs   x0, hcr_el2
 478   ret
 479
 480 // UINTN ArmReadCurrentEL(VOID)
 481 ASM_FUNC(ArmReadCurrentEL)
 482   mrs   x0, CurrentEL
 483   ret
 484
 485 // UINT32 ArmReadCntHctl(VOID)
 486 ASM_FUNC(ArmReadCntHctl)
 487   mrs   x0, cnthctl_el2
 488   ret
 489
 490 // VOID ArmWriteCntHctl(UINT32 CntHctl)
 491 ASM_FUNC(ArmWriteCntHctl)
 492   msr   cnthctl_el2, x0
 493   ret
 494
 495 ASM_FUNCTION_REMOVE_IF_UNREFERENCED