ArmPkg/Library/ArmLib/AArch64/AArch64Support.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011 - 2017, ARM Limited. All rights reserved.
   5 # Copyright (c) 2016, Linaro Limited. All rights reserved.
   6 #
   7 # SPDX-License-Identifier: BSD-2-Clause-Patent
   8 #
   9 #------------------------------------------------------------------------------
  10
  11 #include <Chipset/AArch64.h>
  12 #include <AsmMacroIoLibV8.h>
  13
  14 .set CTRL_M_BIT,      (1 << 0)
  15 .set CTRL_A_BIT,      (1 << 1)
  16 .set CTRL_C_BIT,      (1 << 2)
  17 .set CTRL_SA_BIT,     (1 << 3)
  18 .set CTRL_I_BIT,      (1 << 12)
  19 .set CTRL_V_BIT,      (1 << 12)
  20 .set CPACR_VFP_BITS,  (3 << 20)
  21
  22 ASM_FUNC(ArmInvalidateDataCacheEntryByMVA)
  23   dc      ivac, x0    // Invalidate single data cache line
  24   ret
  25
  26
  27 ASM_FUNC(ArmCleanDataCacheEntryByMVA)
  28   dc      cvac, x0    // Clean single data cache line
  29   ret
  30
  31
  32 ASM_FUNC(ArmCleanDataCacheEntryToPoUByMVA)
  33   dc      cvau, x0    // Clean single data cache line to PoU
  34   ret
  35
  36 ASM_FUNC(ArmInvalidateInstructionCacheEntryToPoUByMVA)
  37   ic      ivau, x0    // Invalidate single instruction cache line to PoU
  38   ret
  39
  40
  41 ASM_FUNC(ArmCleanInvalidateDataCacheEntryByMVA)
  42   dc      civac, x0   // Clean and invalidate single data cache line
  43   ret
  44
  45
  46 ASM_FUNC(ArmInvalidateDataCacheEntryBySetWay)
  47   dc      isw, x0     // Invalidate this line
  48   ret
  49
  50
  51 ASM_FUNC(ArmCleanInvalidateDataCacheEntryBySetWay)
  52   dc      cisw, x0    // Clean and Invalidate this line
  53   ret
  54
  55
  56 ASM_FUNC(ArmCleanDataCacheEntryBySetWay)
  57   dc      csw, x0     // Clean this line
  58   ret
  59
  60
  61 ASM_FUNC(ArmInvalidateInstructionCache)
  62   ic      iallu       // Invalidate entire instruction cache
  63   dsb     sy
  64   isb
  65   ret
  66
  67
  68 ASM_FUNC(ArmEnableMmu)
  69    EL1_OR_EL2_OR_EL3(x1)
  70 1: mrs     x0, sctlr_el1       // Read System control register EL1
  71    b       4f
  72 2: mrs     x0, sctlr_el2       // Read System control register EL2
  73    b       4f
  74 3: mrs     x0, sctlr_el3       // Read System control register EL3
  75 4: orr     x0, x0, #CTRL_M_BIT // Set MMU enable bit
  76    EL1_OR_EL2_OR_EL3(x1)
  77 1: tlbi    vmalle1
  78    dsb     nsh
  79    isb
  80    msr     sctlr_el1, x0       // Write back
  81    b       4f
  82 2: tlbi    alle2
  83    dsb     nsh
  84    isb
  85    msr     sctlr_el2, x0       // Write back
  86    b       4f
  87 3: tlbi    alle3
  88    dsb     nsh
  89    isb
  90    msr     sctlr_el3, x0       // Write back
  91 4: isb
  92    ret
  93
  94
  95 ASM_FUNC(ArmDisableMmu)
  96    EL1_OR_EL2_OR_EL3(x1)
  97 1: mrs     x0, sctlr_el1        // Read System Control Register EL1
  98    b       4f
  99 2: mrs     x0, sctlr_el2        // Read System Control Register EL2
 100    b       4f
 101 3: mrs     x0, sctlr_el3        // Read System Control Register EL3
 102 4: and     x0, x0, #~CTRL_M_BIT  // Clear MMU enable bit
 103    EL1_OR_EL2_OR_EL3(x1)
 104 1: msr     sctlr_el1, x0        // Write back
 105    tlbi    vmalle1
 106    b       4f
 107 2: msr     sctlr_el2, x0        // Write back
 108    tlbi    alle2
 109    b       4f
 110 3: msr     sctlr_el3, x0        // Write back
 111    tlbi    alle3
 112 4: dsb     sy
 113    isb
 114    ret
 115
 116
 117 ASM_FUNC(ArmDisableCachesAndMmu)
 118    EL1_OR_EL2_OR_EL3(x1)
 119 1: mrs     x0, sctlr_el1        // Get control register EL1
 120    b       4f
 121 2: mrs     x0, sctlr_el2        // Get control register EL2
 122    b       4f
 123 3: mrs     x0, sctlr_el3        // Get control register EL3
 124 4: mov     x1, #~(CTRL_M_BIT | CTRL_C_BIT | CTRL_I_BIT)  // Disable MMU, D & I caches
 125    and     x0, x0, x1
 126    EL1_OR_EL2_OR_EL3(x1)
 127 1: msr     sctlr_el1, x0        // Write back control register
 128    b       4f
 129 2: msr     sctlr_el2, x0        // Write back control register
 130    b       4f
 131 3: msr     sctlr_el3, x0        // Write back control register
 132 4: dsb     sy
 133    isb
 134    ret
 135
 136
 137 ASM_FUNC(ArmMmuEnabled)
 138    EL1_OR_EL2_OR_EL3(x1)
 139 1: mrs     x0, sctlr_el1        // Get control register EL1
 140    b       4f
 141 2: mrs     x0, sctlr_el2        // Get control register EL2
 142    b       4f
 143 3: mrs     x0, sctlr_el3        // Get control register EL3
 144 4: and     x0, x0, #CTRL_M_BIT
 145    ret
 146
 147
 148 ASM_FUNC(ArmEnableDataCache)
 149    EL1_OR_EL2_OR_EL3(x1)
 150 1: mrs     x0, sctlr_el1        // Get control register EL1
 151    b       4f
 152 2: mrs     x0, sctlr_el2        // Get control register EL2
 153    b       4f
 154 3: mrs     x0, sctlr_el3        // Get control register EL3
 155 4: orr     x0, x0, #CTRL_C_BIT  // Set C bit
 156    EL1_OR_EL2_OR_EL3(x1)
 157 1: msr     sctlr_el1, x0        // Write back control register
 158    b       4f
 159 2: msr     sctlr_el2, x0        // Write back control register
 160    b       4f
 161 3: msr     sctlr_el3, x0        // Write back control register
 162 4: dsb     sy
 163    isb
 164    ret
 165
 166
 167 ASM_FUNC(ArmDisableDataCache)
 168    EL1_OR_EL2_OR_EL3(x1)
 169 1: mrs     x0, sctlr_el1        // Get control register EL1
 170    b       4f
 171 2: mrs     x0, sctlr_el2        // Get control register EL2
 172    b       4f
 173 3: mrs     x0, sctlr_el3        // Get control register EL3
 174 4: and     x0, x0, #~CTRL_C_BIT  // Clear C bit
 175    EL1_OR_EL2_OR_EL3(x1)
 176 1: msr     sctlr_el1, x0        // Write back control register
 177    b       4f
 178 2: msr     sctlr_el2, x0        // Write back control register
 179    b       4f
 180 3: msr     sctlr_el3, x0        // Write back control register
 181 4: dsb     sy
 182    isb
 183    ret
 184
 185
 186 ASM_FUNC(ArmEnableInstructionCache)
 187    EL1_OR_EL2_OR_EL3(x1)
 188 1: mrs     x0, sctlr_el1        // Get control register EL1
 189    b       4f
 190 2: mrs     x0, sctlr_el2        // Get control register EL2
 191    b       4f
 192 3: mrs     x0, sctlr_el3        // Get control register EL3
 193 4: orr     x0, x0, #CTRL_I_BIT  // Set I bit
 194    EL1_OR_EL2_OR_EL3(x1)
 195 1: msr     sctlr_el1, x0        // Write back control register
 196    b       4f
 197 2: msr     sctlr_el2, x0        // Write back control register
 198    b       4f
 199 3: msr     sctlr_el3, x0        // Write back control register
 200 4: dsb     sy
 201    isb
 202    ret
 203
 204
 205 ASM_FUNC(ArmDisableInstructionCache)
 206    EL1_OR_EL2_OR_EL3(x1)
 207 1: mrs     x0, sctlr_el1        // Get control register EL1
 208    b       4f
 209 2: mrs     x0, sctlr_el2        // Get control register EL2
 210    b       4f
 211 3: mrs     x0, sctlr_el3        // Get control register EL3
 212 4: and     x0, x0, #~CTRL_I_BIT  // Clear I bit
 213    EL1_OR_EL2_OR_EL3(x1)
 214 1: msr     sctlr_el1, x0        // Write back control register
 215    b       4f
 216 2: msr     sctlr_el2, x0        // Write back control register
 217    b       4f
 218 3: msr     sctlr_el3, x0        // Write back control register
 219 4: dsb     sy
 220    isb
 221    ret
 222
 223
 224 ASM_FUNC(ArmEnableAlignmentCheck)
 225    EL1_OR_EL2(x1)
 226 1: mrs     x0, sctlr_el1        // Get control register EL1
 227    b       3f
 228 2: mrs     x0, sctlr_el2        // Get control register EL2
 229 3: orr     x0, x0, #CTRL_A_BIT  // Set A (alignment check) bit
 230    EL1_OR_EL2(x1)
 231 1: msr     sctlr_el1, x0        // Write back control register
 232    b       3f
 233 2: msr     sctlr_el2, x0        // Write back control register
 234 3: dsb     sy
 235    isb
 236    ret
 237
 238
 239 ASM_FUNC(ArmDisableAlignmentCheck)
 240    EL1_OR_EL2_OR_EL3(x1)
 241 1: mrs     x0, sctlr_el1        // Get control register EL1
 242    b       4f
 243 2: mrs     x0, sctlr_el2        // Get control register EL2
 244    b       4f
 245 3: mrs     x0, sctlr_el3        // Get control register EL3
 246 4: and     x0, x0, #~CTRL_A_BIT  // Clear A (alignment check) bit
 247    EL1_OR_EL2_OR_EL3(x1)
 248 1: msr     sctlr_el1, x0        // Write back control register
 249    b       4f
 250 2: msr     sctlr_el2, x0        // Write back control register
 251    b       4f
 252 3: msr     sctlr_el3, x0        // Write back control register
 253 4: dsb     sy
 254    isb
 255    ret
 256
 257 ASM_FUNC(ArmEnableStackAlignmentCheck)
 258    EL1_OR_EL2(x1)
 259 1: mrs     x0, sctlr_el1        // Get control register EL1
 260    b       3f
 261 2: mrs     x0, sctlr_el2        // Get control register EL2
 262 3: orr     x0, x0, #CTRL_SA_BIT // Set SA (stack alignment check) bit
 263    EL1_OR_EL2(x1)
 264 1: msr     sctlr_el1, x0        // Write back control register
 265    b       3f
 266 2: msr     sctlr_el2, x0        // Write back control register
 267 3: dsb     sy
 268    isb
 269    ret
 270
 271
 272 ASM_FUNC(ArmDisableStackAlignmentCheck)
 273    EL1_OR_EL2_OR_EL3(x1)
 274 1: mrs     x0, sctlr_el1        // Get control register EL1
 275    b       4f
 276 2: mrs     x0, sctlr_el2        // Get control register EL2
 277    b       4f
 278 3: mrs     x0, sctlr_el3        // Get control register EL3
 279 4: bic     x0, x0, #CTRL_SA_BIT // Clear SA (stack alignment check) bit
 280    EL1_OR_EL2_OR_EL3(x1)
 281 1: msr     sctlr_el1, x0        // Write back control register
 282    b       4f
 283 2: msr     sctlr_el2, x0        // Write back control register
 284    b       4f
 285 3: msr     sctlr_el3, x0        // Write back control register
 286 4: dsb     sy
 287    isb
 288    ret
 289
 290
 291 // Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now
 292 ASM_FUNC(ArmEnableBranchPrediction)
 293   ret
 294
 295
 296 // Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now.
 297 ASM_FUNC(ArmDisableBranchPrediction)
 298   ret
 299
 300
 301 ASM_FUNC(AArch64AllDataCachesOperation)
 302 // We can use regs 0-7 and 9-15 without having to save/restore.
 303 // Save our link register on the stack. - The stack must always be quad-word aligned
 304   stp   x29, x30, [sp, #-16]!
 305   mov   x29, sp
 306   mov   x1, x0                  // Save Function call in x1
 307   mrs   x6, clidr_el1           // Read EL1 CLIDR
 308   and   x3, x6, #0x7000000      // Mask out all but Level of Coherency (LoC)
 309   lsr   x3, x3, #23             // Left align cache level value - the level is shifted by 1 to the
 310                                 // right to ease the access to CSSELR and the Set/Way operation.
 311   cbz   x3, L_Finished          // No need to clean if LoC is 0
 312   mov   x10, #0                 // Start clean at cache level 0
 313
 314 Loop1:
 315   add   x2, x10, x10, lsr #1    // Work out 3x cachelevel for cache info
 316   lsr   x12, x6, x2             // bottom 3 bits are the Cache type for this level
 317   and   x12, x12, #7            // get those 3 bits alone
 318   cmp   x12, #2                 // what cache at this level?
 319   b.lt  L_Skip                  // no cache or only instruction cache at this level
 320   msr   csselr_el1, x10         // write the Cache Size selection register with current level (CSSELR)
 321   isb                           // isb to sync the change to the CacheSizeID reg
 322   mrs   x12, ccsidr_el1         // reads current Cache Size ID register (CCSIDR)
 323   and   x2, x12, #0x7           // extract the line length field
 324   add   x2, x2, #4              // add 4 for the line length offset (log2 16 bytes)
 325   mov   x4, #0x400
 326   sub   x4, x4, #1
 327   and   x4, x4, x12, lsr #3     // x4 is the max number on the way size (right aligned)
 328   clz   w5, w4                  // w5 is the bit position of the way size increment
 329   mov   x7, #0x00008000
 330   sub   x7, x7, #1
 331   and   x7, x7, x12, lsr #13    // x7 is the max number of the index size (right aligned)
 332
 333 Loop2:
 334   mov   x9, x4                  // x9 working copy of the max way size (right aligned)
 335
 336 Loop3:
 337   lsl   x11, x9, x5
 338   orr   x0, x10, x11            // factor in the way number and cache number
 339   lsl   x11, x7, x2
 340   orr   x0, x0, x11             // factor in the index number
 341
 342   blr   x1                      // Goto requested cache operation
 343
 344   subs  x9, x9, #1              // decrement the way number
 345   b.ge  Loop3
 346   subs  x7, x7, #1              // decrement the index
 347   b.ge  Loop2
 348 L_Skip:
 349   add   x10, x10, #2            // increment the cache number
 350   cmp   x3, x10
 351   b.gt  Loop1
 352
 353 L_Finished:
 354   dsb   sy
 355   isb
 356   ldp   x29, x30, [sp], #0x10
 357   ret
 358
 359
 360 ASM_FUNC(ArmDataMemoryBarrier)
 361   dmb   sy
 362   ret
 363
 364
 365 ASM_FUNC(ArmDataSynchronizationBarrier)
 366   dsb   sy
 367   ret
 368
 369
 370 ASM_FUNC(ArmInstructionSynchronizationBarrier)
 371   isb
 372   ret
 373
 374
 375 ASM_FUNC(ArmWriteVBar)
 376    EL1_OR_EL2_OR_EL3(x1)
 377 1: msr   vbar_el1, x0            // Set the Address of the EL1 Vector Table in the VBAR register
 378    b     4f
 379 2: msr   vbar_el2, x0            // Set the Address of the EL2 Vector Table in the VBAR register
 380    b     4f
 381 3: msr   vbar_el3, x0            // Set the Address of the EL3 Vector Table in the VBAR register
 382 4: isb
 383    ret
 384
 385 ASM_FUNC(ArmReadVBar)
 386    EL1_OR_EL2_OR_EL3(x1)
 387 1: mrs   x0, vbar_el1            // Set the Address of the EL1 Vector Table in the VBAR register
 388    ret
 389 2: mrs   x0, vbar_el2            // Set the Address of the EL2 Vector Table in the VBAR register
 390    ret
 391 3: mrs   x0, vbar_el3            // Set the Address of the EL3 Vector Table in the VBAR register
 392    ret
 393
 394
 395 ASM_FUNC(ArmEnableVFP)
 396   // Check whether floating-point is implemented in the processor.
 397   mov   x1, x30                 // Save LR
 398   bl    ArmReadIdPfr0           // Read EL1 Processor Feature Register (PFR0)
 399   mov   x30, x1                 // Restore LR
 400   ubfx  x0, x0, #16, #4         // Extract the FP bits 16:19
 401   cmp   x0, #0xF                // Check if FP bits are '1111b',
 402                                 // i.e. Floating Point not implemented
 403   b.eq  4f                      // Exit when VFP is not implemented.
 404
 405   // FVP is implemented.
 406   // Make sure VFP exceptions are not trapped (to any exception level).
 407   mrs   x0, cpacr_el1           // Read EL1 Coprocessor Access Control Register (CPACR)
 408   orr   x0, x0, #CPACR_VFP_BITS // Disable FVP traps to EL1
 409   msr   cpacr_el1, x0           // Write back EL1 Coprocessor Access Control Register (CPACR)
 410   mov   x1, #AARCH64_CPTR_TFP   // TFP Bit for trapping VFP Exceptions
 411   EL1_OR_EL2_OR_EL3(x2)
 412 1:ret                           // Not configurable in EL1
 413 2:mrs   x0, cptr_el2            // Disable VFP traps to EL2
 414   bic   x0, x0, x1
 415   msr   cptr_el2, x0
 416   ret
 417 3:mrs   x0, cptr_el3            // Disable VFP traps to EL3
 418   bic   x0, x0, x1
 419   msr   cptr_el3, x0
 420 4:ret
 421
 422
 423 ASM_FUNC(ArmCallWFI)
 424   wfi
 425   ret
 426
 427
 428 ASM_FUNC(ArmReadMpidr)
 429   mrs   x0, mpidr_el1           // read EL1 MPIDR
 430   ret
 431
 432
 433 // Keep old function names for C compatibilty for now. Change later?
 434 ASM_FUNC(ArmReadTpidrurw)
 435   mrs   x0, tpidr_el0           // read tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)
 436   ret
 437
 438
 439 // Keep old function names for C compatibilty for now. Change later?
 440 ASM_FUNC(ArmWriteTpidrurw)
 441   msr   tpidr_el0, x0           // write tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)
 442   ret
 443
 444
 445 // Arch timers are mandatory on AArch64
 446 ASM_FUNC(ArmIsArchTimerImplemented)
 447   mov   x0, #1
 448   ret
 449
 450
 451 ASM_FUNC(ArmReadIdPfr0)
 452   mrs   x0, id_aa64pfr0_el1   // Read ID_AA64PFR0 Register
 453   ret
 454
 455
 456 // Q: id_aa64pfr1_el1 not defined yet. What does this funtion want to access?
 457 // A: used to setup arch timer. Check if we have security extensions, permissions to set stuff.
 458 //    See: ArmPkg/Library/ArmArchTimerLib/AArch64/ArmArchTimerLib.c
 459 //    Not defined yet, but stick in here for now, should read all zeros.
 460 ASM_FUNC(ArmReadIdPfr1)
 461   mrs   x0, id_aa64pfr1_el1   // Read ID_PFR1 Register
 462   ret
 463
 464 // VOID ArmWriteHcr(UINTN Hcr)
 465 ASM_FUNC(ArmWriteHcr)
 466   msr   hcr_el2, x0        // Write the passed HCR value
 467   ret
 468
 469 // UINTN ArmReadHcr(VOID)
 470 ASM_FUNC(ArmReadHcr)
 471   mrs   x0, hcr_el2
 472   ret
 473
 474 // UINTN ArmReadCurrentEL(VOID)
 475 ASM_FUNC(ArmReadCurrentEL)
 476   mrs   x0, CurrentEL
 477   ret
 478
 479 // UINT32 ArmReadCntHctl(VOID)
 480 ASM_FUNC(ArmReadCntHctl)
 481   mrs   x0, cnthctl_el2
 482   ret
 483
 484 // VOID ArmWriteCntHctl(UINT32 CntHctl)
 485 ASM_FUNC(ArmWriteCntHctl)
 486   msr   cnthctl_el2, x0
 487   ret
 488
 489 ASM_FUNCTION_REMOVE_IF_UNREFERENCED