1 #------------------------------------------------------------------------------
3 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
4 # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
6 # This program and the accompanying materials
7 # are licensed and made available under the terms and conditions of the BSD License
8 # which accompanies this distribution. The full text of the license may be found at
9 # http://opensource.org/licenses/bsd-license.php
11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 #------------------------------------------------------------------------------
16 #include <Chipset/AArch64.h>
17 #include <AsmMacroIoLibV8.h>
22 GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
23 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
24 GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
25 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
26 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
27 GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
28 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)
29 GCC_ASM_EXPORT (ArmDrainWriteBuffer)
30 GCC_ASM_EXPORT (ArmEnableMmu)
31 GCC_ASM_EXPORT (ArmDisableMmu)
32 GCC_ASM_EXPORT (ArmDisableCachesAndMmu)
33 GCC_ASM_EXPORT (ArmMmuEnabled)
34 GCC_ASM_EXPORT (ArmEnableDataCache)
35 GCC_ASM_EXPORT (ArmDisableDataCache)
36 GCC_ASM_EXPORT (ArmEnableInstructionCache)
37 GCC_ASM_EXPORT (ArmDisableInstructionCache)
38 GCC_ASM_EXPORT (ArmDisableAlignmentCheck)
39 GCC_ASM_EXPORT (ArmEnableAlignmentCheck)
40 GCC_ASM_EXPORT (ArmEnableBranchPrediction)
41 GCC_ASM_EXPORT (ArmDisableBranchPrediction)
42 GCC_ASM_EXPORT (AArch64AllDataCachesOperation)
43 GCC_ASM_EXPORT (AArch64PerformPoUDataCacheOperation)
44 GCC_ASM_EXPORT (ArmDataMemoryBarrier)
45 GCC_ASM_EXPORT (ArmDataSyncronizationBarrier)
46 GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
47 GCC_ASM_EXPORT (ArmWriteVBar)
48 GCC_ASM_EXPORT (ArmVFPImplemented)
49 GCC_ASM_EXPORT (ArmEnableVFP)
50 GCC_ASM_EXPORT (ArmCallWFI)
51 GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb)
52 GCC_ASM_EXPORT (ArmReadMpidr)
53 GCC_ASM_EXPORT (ArmReadMidr)
54 GCC_ASM_EXPORT (ArmReadTpidrurw)
55 GCC_ASM_EXPORT (ArmWriteTpidrurw)
56 GCC_ASM_EXPORT (ArmIsArchTimerImplemented)
57 GCC_ASM_EXPORT (ArmReadIdPfr0)
58 GCC_ASM_EXPORT (ArmReadIdPfr1)
59 GCC_ASM_EXPORT (ArmWriteHcr)
60 GCC_ASM_EXPORT (ArmReadCurrentEL)
62 .set CTRL_M_BIT, (1 << 0)
63 .set CTRL_A_BIT, (1 << 1)
64 .set CTRL_C_BIT, (1 << 2)
65 .set CTRL_I_BIT, (1 << 12)
66 .set CTRL_V_BIT, (1 << 12)
67 .set CPACR_VFP_BITS, (3 << 20)
69 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
70 dc ivac, x0 // Invalidate single data cache line
76 ASM_PFX(ArmCleanDataCacheEntryByMVA):
77 dc cvac, x0 // Clean single data cache line
83 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
84 dc civac, x0 // Clean and invalidate single data cache line
90 ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
91 dc isw, x0 // Invalidate this line
97 ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
98 dc cisw, x0 // Clean and Invalidate this line
104 ASM_PFX(ArmCleanDataCacheEntryBySetWay):
105 dc csw, x0 // Clean this line
111 ASM_PFX(ArmInvalidateInstructionCache):
112 ic iallu // Invalidate entire instruction cache
118 ASM_PFX(ArmEnableMmu):
119 EL1_OR_EL2_OR_EL3(x1)
120 1: mrs x0, sctlr_el1 // Read System control register EL1
122 2: mrs x0, sctlr_el2 // Read System control register EL2
124 3: mrs x0, sctlr_el3 // Read System control register EL3
125 4: orr x0, x0, #CTRL_M_BIT // Set MMU enable bit
126 EL1_OR_EL2_OR_EL3(x1)
129 msr sctlr_el1, x0 // Write back
133 msr sctlr_el2, x0 // Write back
137 msr sctlr_el3, x0 // Write back
143 ASM_PFX(ArmDisableMmu):
144 EL1_OR_EL2_OR_EL3(x1)
145 1: mrs x0, sctlr_el1 // Read System Control Register EL1
147 2: mrs x0, sctlr_el2 // Read System Control Register EL2
149 3: mrs x0, sctlr_el3 // Read System Control Register EL3
150 4: bic x0, x0, #CTRL_M_BIT // Clear MMU enable bit
151 EL1_OR_EL2_OR_EL3(x1)
152 1: msr sctlr_el1, x0 // Write back
155 2: msr sctlr_el2, x0 // Write back
158 3: msr sctlr_el3, x0 // Write back
165 ASM_PFX(ArmDisableCachesAndMmu):
166 EL1_OR_EL2_OR_EL3(x1)
167 1: mrs x0, sctlr_el1 // Get control register EL1
169 2: mrs x0, sctlr_el2 // Get control register EL2
171 3: mrs x0, sctlr_el3 // Get control register EL3
172 4: bic x0, x0, #CTRL_M_BIT // Disable MMU
173 bic x0, x0, #CTRL_C_BIT // Disable D Cache
174 bic x0, x0, #CTRL_I_BIT // Disable I Cache
175 EL1_OR_EL2_OR_EL3(x1)
176 1: msr sctlr_el1, x0 // Write back control register
178 2: msr sctlr_el2, x0 // Write back control register
180 3: msr sctlr_el3, x0 // Write back control register
186 ASM_PFX(ArmMmuEnabled):
187 EL1_OR_EL2_OR_EL3(x1)
188 1: mrs x0, sctlr_el1 // Get control register EL1
190 2: mrs x0, sctlr_el2 // Get control register EL2
192 3: mrs x0, sctlr_el3 // Get control register EL3
193 4: and x0, x0, #CTRL_M_BIT
197 ASM_PFX(ArmEnableDataCache):
198 EL1_OR_EL2_OR_EL3(x1)
199 1: mrs x0, sctlr_el1 // Get control register EL1
201 2: mrs x0, sctlr_el2 // Get control register EL2
203 3: mrs x0, sctlr_el3 // Get control register EL3
204 4: orr x0, x0, #CTRL_C_BIT // Set C bit
205 EL1_OR_EL2_OR_EL3(x1)
206 1: msr sctlr_el1, x0 // Write back control register
208 2: msr sctlr_el2, x0 // Write back control register
210 3: msr sctlr_el3, x0 // Write back control register
216 ASM_PFX(ArmDisableDataCache):
217 EL1_OR_EL2_OR_EL3(x1)
218 1: mrs x0, sctlr_el1 // Get control register EL1
220 2: mrs x0, sctlr_el2 // Get control register EL2
222 3: mrs x0, sctlr_el3 // Get control register EL3
223 4: bic x0, x0, #CTRL_C_BIT // Clear C bit
224 EL1_OR_EL2_OR_EL3(x1)
225 1: msr sctlr_el1, x0 // Write back control register
227 2: msr sctlr_el2, x0 // Write back control register
229 3: msr sctlr_el3, x0 // Write back control register
235 ASM_PFX(ArmEnableInstructionCache):
236 EL1_OR_EL2_OR_EL3(x1)
237 1: mrs x0, sctlr_el1 // Get control register EL1
239 2: mrs x0, sctlr_el2 // Get control register EL2
241 3: mrs x0, sctlr_el3 // Get control register EL3
242 4: orr x0, x0, #CTRL_I_BIT // Set I bit
243 EL1_OR_EL2_OR_EL3(x1)
244 1: msr sctlr_el1, x0 // Write back control register
246 2: msr sctlr_el2, x0 // Write back control register
248 3: msr sctlr_el3, x0 // Write back control register
254 ASM_PFX(ArmDisableInstructionCache):
255 EL1_OR_EL2_OR_EL3(x1)
256 1: mrs x0, sctlr_el1 // Get control register EL1
258 2: mrs x0, sctlr_el2 // Get control register EL2
260 3: mrs x0, sctlr_el3 // Get control register EL3
261 4: bic x0, x0, #CTRL_I_BIT // Clear I bit
262 EL1_OR_EL2_OR_EL3(x1)
263 1: msr sctlr_el1, x0 // Write back control register
265 2: msr sctlr_el2, x0 // Write back control register
267 3: msr sctlr_el3, x0 // Write back control register
273 ASM_PFX(ArmEnableAlignmentCheck):
275 1: mrs x0, sctlr_el1 // Get control register EL1
277 2: mrs x0, sctlr_el2 // Get control register EL2
278 3: orr x0, x0, #CTRL_A_BIT // Set A (alignment check) bit
280 1: msr sctlr_el1, x0 // Write back control register
282 2: msr sctlr_el2, x0 // Write back control register
288 ASM_PFX(ArmDisableAlignmentCheck):
289 EL1_OR_EL2_OR_EL3(x1)
290 1: mrs x0, sctlr_el1 // Get control register EL1
292 2: mrs x0, sctlr_el2 // Get control register EL2
294 3: mrs x0, sctlr_el3 // Get control register EL3
295 4: bic x0, x0, #CTRL_A_BIT // Clear A (alignment check) bit
296 EL1_OR_EL2_OR_EL3(x1)
297 1: msr sctlr_el1, x0 // Write back control register
299 2: msr sctlr_el2, x0 // Write back control register
301 3: msr sctlr_el3, x0 // Write back control register
307 // Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now
308 ASM_PFX(ArmEnableBranchPrediction):
312 // Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now.
313 ASM_PFX(ArmDisableBranchPrediction):
317 ASM_PFX(AArch64AllDataCachesOperation):
318 // We can use regs 0-7 and 9-15 without having to save/restore.
319 // Save our link register on the stack.
320 str x30, [sp, #-0x10]!
321 mov x1, x0 // Save Function call in x1
322 mrs x6, clidr_el1 // Read EL1 CLIDR
323 and x3, x6, #0x7000000 // Mask out all but Level of Coherency (LoC)
324 lsr x3, x3, #23 // Left align cache level value - the level is shifted by 1 to the
325 // right to ease the access to CSSELR and the Set/Way operation.
326 cbz x3, L_Finished // No need to clean if LoC is 0
327 mov x10, #0 // Start clean at cache level 0
330 ASM_PFX(AArch64PerformPoUDataCacheOperation):
331 // We can use regs 0-7 and 9-15 without having to save/restore.
332 // Save our link register on the stack.
333 str x30, [sp, #-0x10]!
334 mov x1, x0 // Save Function call in x1
335 mrs x6, clidr_el1 // Read EL1 CLIDR
336 and x3, x6, #0x38000000 // Mask out all but Point of Unification (PoU)
337 lsr x3, x3, #26 // Left align cache level value - the level is shifted by 1 to the
338 // right to ease the access to CSSELR and the Set/Way operation.
339 cbz x3, L_Finished // No need to clean if LoC is 0
340 mov x10, #0 // Start clean at cache level 0
343 add x2, x10, x10, lsr #1 // Work out 3x cachelevel for cache info
344 lsr x12, x6, x2 // bottom 3 bits are the Cache type for this level
345 and x12, x12, #7 // get those 3 bits alone
346 cmp x12, #2 // what cache at this level?
347 b.lt L_Skip // no cache or only instruction cache at this level
348 msr csselr_el1, x10 // write the Cache Size selection register with current level (CSSELR)
349 isb // isb to sync the change to the CacheSizeID reg
350 mrs x12, ccsidr_el1 // reads current Cache Size ID register (CCSIDR)
351 and x2, x12, #0x7 // extract the line length field
352 add x2, x2, #4 // add 4 for the line length offset (log2 16 bytes)
355 and x4, x4, x12, lsr #3 // x4 is the max number on the way size (right aligned)
356 clz w5, w4 // w5 is the bit position of the way size increment
359 and x7, x7, x12, lsr #13 // x7 is the max number of the index size (right aligned)
362 mov x9, x4 // x9 working copy of the max way size (right aligned)
366 orr x0, x10, x11 // factor in the way number and cache number
368 orr x0, x0, x11 // factor in the index number
370 blr x1 // Goto requested cache operation
372 subs x9, x9, #1 // decrement the way number
374 subs x7, x7, #1 // decrement the index
377 add x10, x10, #2 // increment the cache number
388 ASM_PFX(ArmDataMemoryBarrier):
393 ASM_PFX(ArmDataSyncronizationBarrier):
394 ASM_PFX(ArmDrainWriteBuffer):
399 ASM_PFX(ArmInstructionSynchronizationBarrier):
404 ASM_PFX(ArmWriteVBar):
405 EL1_OR_EL2_OR_EL3(x1)
406 1: msr vbar_el1, x0 // Set the Address of the EL1 Vector Table in the VBAR register
408 2: msr vbar_el2, x0 // Set the Address of the EL2 Vector Table in the VBAR register
410 3: msr vbar_el3, x0 // Set the Address of the EL3 Vector Table in the VBAR register
414 ASM_PFX(ArmEnableVFP):
415 // Check whether floating-point is implemented in the processor.
416 mov x1, x30 // Save LR
417 bl ArmReadIdPfr0 // Read EL1 Processor Feature Register (PFR0)
418 mov x30, x1 // Restore LR
419 ands x0, x0, #AARCH64_PFR0_FP// Extract bits indicating VFP implementation
420 cmp x0, #0 // VFP is implemented if '0'.
421 b.ne 4f // Exit if VFP not implemented.
422 // FVP is implemented.
423 // Make sure VFP exceptions are not trapped (to any exception level).
424 mrs x0, cpacr_el1 // Read EL1 Coprocessor Access Control Register (CPACR)
425 orr x0, x0, #CPACR_VFP_BITS // Disable FVP traps to EL1
426 msr cpacr_el1, x0 // Write back EL1 Coprocessor Access Control Register (CPACR)
427 mov x1, #AARCH64_CPTR_TFP // TFP Bit for trapping VFP Exceptions
428 EL1_OR_EL2_OR_EL3(x2)
429 1:ret // Not configurable in EL1
430 2:mrs x0, cptr_el2 // Disable VFP traps to EL2
434 3:mrs x0, cptr_el3 // Disable VFP traps to EL3
445 ASM_PFX(ArmInvalidateInstructionAndDataTlb):
446 EL1_OR_EL2_OR_EL3(x0)
457 ASM_PFX(ArmReadMpidr):
458 mrs x0, mpidr_el1 // read EL1 MPIDR
461 ASM_PFX(ArmReadMidr):
462 mrs x0, midr_el1 // Read Main ID Register
465 // Keep old function names for C compatibilty for now. Change later?
466 ASM_PFX(ArmReadTpidrurw):
467 mrs x0, tpidr_el0 // read tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)
471 // Keep old function names for C compatibilty for now. Change later?
472 ASM_PFX(ArmWriteTpidrurw):
473 msr tpidr_el0, x0 // write tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)
477 // Arch timers are mandatory on AArch64
478 ASM_PFX(ArmIsArchTimerImplemented):
483 ASM_PFX(ArmReadIdPfr0):
484 mrs x0, id_aa64pfr0_el1 // Read ID_AA64PFR0 Register
488 // Q: id_aa64pfr1_el1 not defined yet. What does this funtion want to access?
489 // A: used to setup arch timer. Check if we have security extensions, permissions to set stuff.
490 // See: ArmPkg/Library/ArmArchTimerLib/AArch64/ArmArchTimerLib.c
491 // Not defined yet, but stick in here for now, should read all zeros.
492 ASM_PFX(ArmReadIdPfr1):
493 mrs x0, id_aa64pfr1_el1 // Read ID_PFR1 Register
496 // VOID ArmWriteHcr(UINTN Hcr)
497 ASM_PFX(ArmWriteHcr):
498 msr hcr_el2, x0 // Write the passed HCR value
501 // UINTN ArmReadCurrentEL(VOID)
502 ASM_PFX(ArmReadCurrentEL):
509 ASM_FUNCTION_REMOVE_IF_UNREFERENCED