ArmPkg/Library/ArmLib/AArch64/AArch64Support.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
   5 #
   6 # This program and the accompanying materials
   7 # are licensed and made available under the terms and conditions of the BSD License
   8 # which accompanies this distribution.  The full text of the license may be found at
   9 # http://opensource.org/licenses/bsd-license.php
  10 #
  11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 #
  14 #------------------------------------------------------------------------------
  15
  16 #include <Chipset/AArch64.h>
  17 #include <AsmMacroIoLibV8.h>
  18
  19 .text
  20 .align 3
  21
  22 GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
  23 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
  24 GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
  25 GCC_ASM_EXPORT (ArmCleanDataCacheEntryToPoUByMVA)
  26 GCC_ASM_EXPORT (ArmInvalidateInstructionCacheEntryToPoUByMVA)
  27 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
  28 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
  29 GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
  30 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)
  31 GCC_ASM_EXPORT (ArmEnableMmu)
  32 GCC_ASM_EXPORT (ArmDisableMmu)
  33 GCC_ASM_EXPORT (ArmDisableCachesAndMmu)
  34 GCC_ASM_EXPORT (ArmMmuEnabled)
  35 GCC_ASM_EXPORT (ArmEnableDataCache)
  36 GCC_ASM_EXPORT (ArmDisableDataCache)
  37 GCC_ASM_EXPORT (ArmEnableInstructionCache)
  38 GCC_ASM_EXPORT (ArmDisableInstructionCache)
  39 GCC_ASM_EXPORT (ArmDisableAlignmentCheck)
  40 GCC_ASM_EXPORT (ArmEnableAlignmentCheck)
  41 GCC_ASM_EXPORT (ArmEnableBranchPrediction)
  42 GCC_ASM_EXPORT (ArmDisableBranchPrediction)
  43 GCC_ASM_EXPORT (AArch64AllDataCachesOperation)
  44 GCC_ASM_EXPORT (ArmDataMemoryBarrier)
  45 GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)
  46 GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
  47 GCC_ASM_EXPORT (ArmWriteVBar)
  48 GCC_ASM_EXPORT (ArmReadVBar)
  49 GCC_ASM_EXPORT (ArmEnableVFP)
  50 GCC_ASM_EXPORT (ArmCallWFI)
  51 GCC_ASM_EXPORT (ArmReadMpidr)
  52 GCC_ASM_EXPORT (ArmReadTpidrurw)
  53 GCC_ASM_EXPORT (ArmWriteTpidrurw)
  54 GCC_ASM_EXPORT (ArmIsArchTimerImplemented)
  55 GCC_ASM_EXPORT (ArmReadIdPfr0)
  56 GCC_ASM_EXPORT (ArmReadIdPfr1)
  57 GCC_ASM_EXPORT (ArmWriteHcr)
  58 GCC_ASM_EXPORT (ArmReadHcr)
  59 GCC_ASM_EXPORT (ArmReadCurrentEL)
  60 GCC_ASM_EXPORT (ArmReplaceLiveTranslationEntry)
  61 GCC_ASM_EXPORT (ArmReplaceLiveTranslationEntrySize)
  62
  63 .set CTRL_M_BIT,      (1 << 0)
  64 .set CTRL_A_BIT,      (1 << 1)
  65 .set CTRL_C_BIT,      (1 << 2)
  66 .set CTRL_I_BIT,      (1 << 12)
  67 .set CTRL_V_BIT,      (1 << 12)
  68 .set CPACR_VFP_BITS,  (3 << 20)
  69
  70 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
  71   dc      ivac, x0    // Invalidate single data cache line
  72   ret
  73
  74
  75 ASM_PFX(ArmCleanDataCacheEntryByMVA):
  76   dc      cvac, x0    // Clean single data cache line
  77   ret
  78
  79
  80 ASM_PFX(ArmCleanDataCacheEntryToPoUByMVA):
  81   dc      cvau, x0    // Clean single data cache line to PoU
  82   ret
  83
  84 ASM_PFX(ArmInvalidateInstructionCacheEntryToPoUByMVA):
  85   ic      ivau, x0    // Invalidate single instruction cache line to PoU
  86   ret
  87
  88
  89 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
  90   dc      civac, x0   // Clean and invalidate single data cache line
  91   ret
  92
  93
  94 ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
  95   dc      isw, x0     // Invalidate this line
  96   ret
  97
  98
  99 ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
 100   dc      cisw, x0    // Clean and Invalidate this line
 101   ret
 102
 103
 104 ASM_PFX(ArmCleanDataCacheEntryBySetWay):
 105   dc      csw, x0     // Clean this line
 106   ret
 107
 108
 109 ASM_PFX(ArmInvalidateInstructionCache):
 110   ic      iallu       // Invalidate entire instruction cache
 111   dsb     sy
 112   isb
 113   ret
 114
 115
 116 ASM_PFX(ArmEnableMmu):
 117    EL1_OR_EL2_OR_EL3(x1)
 118 1: mrs     x0, sctlr_el1       // Read System control register EL1
 119    b       4f
 120 2: mrs     x0, sctlr_el2       // Read System control register EL2
 121    b       4f
 122 3: mrs     x0, sctlr_el3       // Read System control register EL3
 123 4: orr     x0, x0, #CTRL_M_BIT // Set MMU enable bit
 124    EL1_OR_EL2_OR_EL3(x1)
 125 1: tlbi    vmalle1
 126    dsb     nsh
 127    isb
 128    msr     sctlr_el1, x0       // Write back
 129    b       4f
 130 2: tlbi    alle2
 131    dsb     nsh
 132    isb
 133    msr     sctlr_el2, x0       // Write back
 134    b       4f
 135 3: tlbi    alle3
 136    dsb     nsh
 137    isb
 138    msr     sctlr_el3, x0       // Write back
 139 4: isb
 140    ret
 141
 142
 143 ASM_PFX(ArmDisableMmu):
 144    EL1_OR_EL2_OR_EL3(x1)
 145 1: mrs     x0, sctlr_el1        // Read System Control Register EL1
 146    b       4f
 147 2: mrs     x0, sctlr_el2        // Read System Control Register EL2
 148    b       4f
 149 3: mrs     x0, sctlr_el3        // Read System Control Register EL3
 150 4: and     x0, x0, #~CTRL_M_BIT  // Clear MMU enable bit
 151    EL1_OR_EL2_OR_EL3(x1)
 152 1: msr     sctlr_el1, x0        // Write back
 153    tlbi    vmalle1
 154    b       4f
 155 2: msr     sctlr_el2, x0        // Write back
 156    tlbi    alle2
 157    b       4f
 158 3: msr     sctlr_el3, x0        // Write back
 159    tlbi    alle3
 160 4: dsb     sy
 161    isb
 162    ret
 163
 164
 165 ASM_PFX(ArmDisableCachesAndMmu):
 166    EL1_OR_EL2_OR_EL3(x1)
 167 1: mrs     x0, sctlr_el1        // Get control register EL1
 168    b       4f
 169 2: mrs     x0, sctlr_el2        // Get control register EL2
 170    b       4f
 171 3: mrs     x0, sctlr_el3        // Get control register EL3
 172 4: mov     x1, #~(CTRL_M_BIT | CTRL_C_BIT | CTRL_I_BIT)  // Disable MMU, D & I caches
 173    and     x0, x0, x1
 174    EL1_OR_EL2_OR_EL3(x1)
 175 1: msr     sctlr_el1, x0        // Write back control register
 176    b       4f
 177 2: msr     sctlr_el2, x0        // Write back control register
 178    b       4f
 179 3: msr     sctlr_el3, x0        // Write back control register
 180 4: dsb     sy
 181    isb
 182    ret
 183
 184
 185 ASM_PFX(ArmMmuEnabled):
 186    EL1_OR_EL2_OR_EL3(x1)
 187 1: mrs     x0, sctlr_el1        // Get control register EL1
 188    b       4f
 189 2: mrs     x0, sctlr_el2        // Get control register EL2
 190    b       4f
 191 3: mrs     x0, sctlr_el3        // Get control register EL3
 192 4: and     x0, x0, #CTRL_M_BIT
 193    ret
 194
 195
 196 ASM_PFX(ArmEnableDataCache):
 197    EL1_OR_EL2_OR_EL3(x1)
 198 1: mrs     x0, sctlr_el1        // Get control register EL1
 199    b       4f
 200 2: mrs     x0, sctlr_el2        // Get control register EL2
 201    b       4f
 202 3: mrs     x0, sctlr_el3        // Get control register EL3
 203 4: orr     x0, x0, #CTRL_C_BIT  // Set C bit
 204    EL1_OR_EL2_OR_EL3(x1)
 205 1: msr     sctlr_el1, x0        // Write back control register
 206    b       4f
 207 2: msr     sctlr_el2, x0        // Write back control register
 208    b       4f
 209 3: msr     sctlr_el3, x0        // Write back control register
 210 4: dsb     sy
 211    isb
 212    ret
 213
 214
 215 ASM_PFX(ArmDisableDataCache):
 216    EL1_OR_EL2_OR_EL3(x1)
 217 1: mrs     x0, sctlr_el1        // Get control register EL1
 218    b       4f
 219 2: mrs     x0, sctlr_el2        // Get control register EL2
 220    b       4f
 221 3: mrs     x0, sctlr_el3        // Get control register EL3
 222 4: and     x0, x0, #~CTRL_C_BIT  // Clear C bit
 223    EL1_OR_EL2_OR_EL3(x1)
 224 1: msr     sctlr_el1, x0        // Write back control register
 225    b       4f
 226 2: msr     sctlr_el2, x0        // Write back control register
 227    b       4f
 228 3: msr     sctlr_el3, x0        // Write back control register
 229 4: dsb     sy
 230    isb
 231    ret
 232
 233
 234 ASM_PFX(ArmEnableInstructionCache):
 235    EL1_OR_EL2_OR_EL3(x1)
 236 1: mrs     x0, sctlr_el1        // Get control register EL1
 237    b       4f
 238 2: mrs     x0, sctlr_el2        // Get control register EL2
 239    b       4f
 240 3: mrs     x0, sctlr_el3        // Get control register EL3
 241 4: orr     x0, x0, #CTRL_I_BIT  // Set I bit
 242    EL1_OR_EL2_OR_EL3(x1)
 243 1: msr     sctlr_el1, x0        // Write back control register
 244    b       4f
 245 2: msr     sctlr_el2, x0        // Write back control register
 246    b       4f
 247 3: msr     sctlr_el3, x0        // Write back control register
 248 4: dsb     sy
 249    isb
 250    ret
 251
 252
 253 ASM_PFX(ArmDisableInstructionCache):
 254    EL1_OR_EL2_OR_EL3(x1)
 255 1: mrs     x0, sctlr_el1        // Get control register EL1
 256    b       4f
 257 2: mrs     x0, sctlr_el2        // Get control register EL2
 258    b       4f
 259 3: mrs     x0, sctlr_el3        // Get control register EL3
 260 4: and     x0, x0, #~CTRL_I_BIT  // Clear I bit
 261    EL1_OR_EL2_OR_EL3(x1)
 262 1: msr     sctlr_el1, x0        // Write back control register
 263    b       4f
 264 2: msr     sctlr_el2, x0        // Write back control register
 265    b       4f
 266 3: msr     sctlr_el3, x0        // Write back control register
 267 4: dsb     sy
 268    isb
 269    ret
 270
 271
 272 ASM_PFX(ArmEnableAlignmentCheck):
 273    EL1_OR_EL2(x1)
 274 1: mrs     x0, sctlr_el1        // Get control register EL1
 275    b       3f
 276 2: mrs     x0, sctlr_el2        // Get control register EL2
 277 3: orr     x0, x0, #CTRL_A_BIT  // Set A (alignment check) bit
 278    EL1_OR_EL2(x1)
 279 1: msr     sctlr_el1, x0        // Write back control register
 280    b       3f
 281 2: msr     sctlr_el2, x0        // Write back control register
 282 3: dsb     sy
 283    isb
 284    ret
 285
 286
 287 ASM_PFX(ArmDisableAlignmentCheck):
 288    EL1_OR_EL2_OR_EL3(x1)
 289 1: mrs     x0, sctlr_el1        // Get control register EL1
 290    b       4f
 291 2: mrs     x0, sctlr_el2        // Get control register EL2
 292    b       4f
 293 3: mrs     x0, sctlr_el3        // Get control register EL3
 294 4: and     x0, x0, #~CTRL_A_BIT  // Clear A (alignment check) bit
 295    EL1_OR_EL2_OR_EL3(x1)
 296 1: msr     sctlr_el1, x0        // Write back control register
 297    b       4f
 298 2: msr     sctlr_el2, x0        // Write back control register
 299    b       4f
 300 3: msr     sctlr_el3, x0        // Write back control register
 301 4: dsb     sy
 302    isb
 303    ret
 304
 305
 306 // Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now
 307 ASM_PFX(ArmEnableBranchPrediction):
 308   ret
 309
 310
 311 // Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now.
 312 ASM_PFX(ArmDisableBranchPrediction):
 313   ret
 314
 315
 316 ASM_PFX(AArch64AllDataCachesOperation):
 317 // We can use regs 0-7 and 9-15 without having to save/restore.
 318 // Save our link register on the stack. - The stack must always be quad-word aligned
 319   str   x30, [sp, #-16]!
 320   mov   x1, x0                  // Save Function call in x1
 321   mrs   x6, clidr_el1           // Read EL1 CLIDR
 322   and   x3, x6, #0x7000000      // Mask out all but Level of Coherency (LoC)
 323   lsr   x3, x3, #23             // Left align cache level value - the level is shifted by 1 to the
 324                                 // right to ease the access to CSSELR and the Set/Way operation.
 325   cbz   x3, L_Finished          // No need to clean if LoC is 0
 326   mov   x10, #0                 // Start clean at cache level 0
 327
 328 Loop1:
 329   add   x2, x10, x10, lsr #1    // Work out 3x cachelevel for cache info
 330   lsr   x12, x6, x2             // bottom 3 bits are the Cache type for this level
 331   and   x12, x12, #7            // get those 3 bits alone
 332   cmp   x12, #2                 // what cache at this level?
 333   b.lt  L_Skip                  // no cache or only instruction cache at this level
 334   msr   csselr_el1, x10         // write the Cache Size selection register with current level (CSSELR)
 335   isb                           // isb to sync the change to the CacheSizeID reg
 336   mrs   x12, ccsidr_el1         // reads current Cache Size ID register (CCSIDR)
 337   and   x2, x12, #0x7           // extract the line length field
 338   add   x2, x2, #4              // add 4 for the line length offset (log2 16 bytes)
 339   mov   x4, #0x400
 340   sub   x4, x4, #1
 341   and   x4, x4, x12, lsr #3     // x4 is the max number on the way size (right aligned)
 342   clz   w5, w4                  // w5 is the bit position of the way size increment
 343   mov   x7, #0x00008000
 344   sub   x7, x7, #1
 345   and   x7, x7, x12, lsr #13    // x7 is the max number of the index size (right aligned)
 346
 347 Loop2:
 348   mov   x9, x4                  // x9 working copy of the max way size (right aligned)
 349
 350 Loop3:
 351   lsl   x11, x9, x5
 352   orr   x0, x10, x11            // factor in the way number and cache number
 353   lsl   x11, x7, x2
 354   orr   x0, x0, x11             // factor in the index number
 355
 356   blr   x1                      // Goto requested cache operation
 357
 358   subs  x9, x9, #1              // decrement the way number
 359   b.ge  Loop3
 360   subs  x7, x7, #1              // decrement the index
 361   b.ge  Loop2
 362 L_Skip:
 363   add   x10, x10, #2            // increment the cache number
 364   cmp   x3, x10
 365   b.gt  Loop1
 366
 367 L_Finished:
 368   dsb   sy
 369   isb
 370   ldr   x30, [sp], #0x10
 371   ret
 372
 373
 374 ASM_PFX(ArmDataMemoryBarrier):
 375   dmb   sy
 376   ret
 377
 378
 379 ASM_PFX(ArmDataSynchronizationBarrier):
 380   dsb   sy
 381   ret
 382
 383
 384 ASM_PFX(ArmInstructionSynchronizationBarrier):
 385   isb
 386   ret
 387
 388
 389 ASM_PFX(ArmWriteVBar):
 390    EL1_OR_EL2_OR_EL3(x1)
 391 1: msr   vbar_el1, x0            // Set the Address of the EL1 Vector Table in the VBAR register
 392    b     4f
 393 2: msr   vbar_el2, x0            // Set the Address of the EL2 Vector Table in the VBAR register
 394    b     4f
 395 3: msr   vbar_el3, x0            // Set the Address of the EL3 Vector Table in the VBAR register
 396 4: isb
 397    ret
 398
 399 ASM_PFX(ArmReadVBar):
 400    EL1_OR_EL2_OR_EL3(x1)
 401 1: mrs   x0, vbar_el1            // Set the Address of the EL1 Vector Table in the VBAR register
 402    ret
 403 2: mrs   x0, vbar_el2            // Set the Address of the EL2 Vector Table in the VBAR register
 404    ret
 405 3: mrs   x0, vbar_el3            // Set the Address of the EL3 Vector Table in the VBAR register
 406    ret
 407
 408
 409 ASM_PFX(ArmEnableVFP):
 410   // Check whether floating-point is implemented in the processor.
 411   mov   x1, x30                 // Save LR
 412   bl    ArmReadIdPfr0           // Read EL1 Processor Feature Register (PFR0)
 413   mov   x30, x1                 // Restore LR
 414   ands  x0, x0, #AARCH64_PFR0_FP// Extract bits indicating VFP implementation
 415   cmp   x0, #0                  // VFP is implemented if '0'.
 416   b.ne  4f                      // Exit if VFP not implemented.
 417   // FVP is implemented.
 418   // Make sure VFP exceptions are not trapped (to any exception level).
 419   mrs   x0, cpacr_el1           // Read EL1 Coprocessor Access Control Register (CPACR)
 420   orr   x0, x0, #CPACR_VFP_BITS // Disable FVP traps to EL1
 421   msr   cpacr_el1, x0           // Write back EL1 Coprocessor Access Control Register (CPACR)
 422   mov   x1, #AARCH64_CPTR_TFP   // TFP Bit for trapping VFP Exceptions
 423   EL1_OR_EL2_OR_EL3(x2)
 424 1:ret                           // Not configurable in EL1
 425 2:mrs   x0, cptr_el2            // Disable VFP traps to EL2
 426   bic   x0, x0, x1
 427   msr   cptr_el2, x0
 428   ret
 429 3:mrs   x0, cptr_el3            // Disable VFP traps to EL3
 430   bic   x0, x0, x1
 431   msr   cptr_el3, x0
 432 4:ret
 433
 434
 435 ASM_PFX(ArmCallWFI):
 436   wfi
 437   ret
 438
 439
 440 ASM_PFX(ArmReadMpidr):
 441   mrs   x0, mpidr_el1           // read EL1 MPIDR
 442   ret
 443
 444
 445 // Keep old function names for C compatibilty for now. Change later?
 446 ASM_PFX(ArmReadTpidrurw):
 447   mrs   x0, tpidr_el0           // read tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)
 448   ret
 449
 450
 451 // Keep old function names for C compatibilty for now. Change later?
 452 ASM_PFX(ArmWriteTpidrurw):
 453   msr   tpidr_el0, x0           // write tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)
 454   ret
 455
 456
 457 // Arch timers are mandatory on AArch64
 458 ASM_PFX(ArmIsArchTimerImplemented):
 459   mov   x0, #1
 460   ret
 461
 462
 463 ASM_PFX(ArmReadIdPfr0):
 464   mrs   x0, id_aa64pfr0_el1   // Read ID_AA64PFR0 Register
 465   ret
 466
 467
 468 // Q: id_aa64pfr1_el1 not defined yet. What does this funtion want to access?
 469 // A: used to setup arch timer. Check if we have security extensions, permissions to set stuff.
 470 //    See: ArmPkg/Library/ArmArchTimerLib/AArch64/ArmArchTimerLib.c
 471 //    Not defined yet, but stick in here for now, should read all zeros.
 472 ASM_PFX(ArmReadIdPfr1):
 473   mrs   x0, id_aa64pfr1_el1   // Read ID_PFR1 Register
 474   ret
 475
 476 // VOID ArmWriteHcr(UINTN Hcr)
 477 ASM_PFX(ArmWriteHcr):
 478   msr   hcr_el2, x0        // Write the passed HCR value
 479   ret
 480
 481 // UINTN ArmReadHcr(VOID)
 482 ASM_PFX(ArmReadHcr):
 483   mrs   x0, hcr_el2
 484   ret
 485
 486 // UINTN ArmReadCurrentEL(VOID)
 487 ASM_PFX(ArmReadCurrentEL):
 488   mrs   x0, CurrentEL
 489   ret
 490
 491
 492   .macro __replace_entry, el
 493
 494   // disable the MMU
 495   mrs   x8, sctlr_el\el
 496   bic   x9, x8, #CTRL_M_BIT
 497   msr   sctlr_el\el, x9
 498   isb
 499
 500   // write updated entry
 501   str   x1, [x0]
 502
 503   // invalidate again to get rid of stale clean cachelines that may
 504   // have been filled speculatively since the last invalidate
 505   dmb   sy
 506   dc    ivac, x0
 507
 508   // flush the TLBs
 509   .if   \el == 1
 510   tlbi  vmalle1
 511   .else
 512   tlbi  alle\el
 513   .endif
 514   dsb   sy
 515
 516   // re-enable the MMU
 517   msr   sctlr_el\el, x8
 518   isb
 519   .endm
 520
 521 //VOID
 522 //ArmReplaceLiveTranslationEntry (
 523 //  IN  UINT64  *Entry,
 524 //  IN  UINT64  Value
 525 //  )
 526 ASM_PFX(ArmReplaceLiveTranslationEntry):
 527
 528   // disable interrupts
 529   mrs   x2, daif
 530   msr   daifset, #0xf
 531   isb
 532
 533   // clean and invalidate first so that we don't clobber
 534   // adjacent entries that are dirty in the caches
 535   dc    civac, x0
 536   dsb   ish
 537
 538   EL1_OR_EL2_OR_EL3(x3)
 539 1:__replace_entry 1
 540   b     4f
 541 2:__replace_entry 2
 542   b     4f
 543 3:__replace_entry 3
 544
 545 4:msr   daif, x2
 546   ret
 547
 548 ASM_PFX(ArmReplaceLiveTranslationEntrySize):
 549   .long   . - ArmReplaceLiveTranslationEntry
 550
 551 ASM_FUNCTION_REMOVE_IF_UNREFERENCED