1 #------------------------------------------------------------------------------
3 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
4 # Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.
6 # This program and the accompanying materials
7 # are licensed and made available under the terms and conditions of the BSD License
8 # which accompanies this distribution. The full text of the license may be found at
9 # http://opensource.org/licenses/bsd-license.php
11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 #------------------------------------------------------------------------------
16 #include <Chipset/AArch64.h>
17 #include <AsmMacroIoLibV8.h>
22 GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
23 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
24 GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
25 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
26 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
27 GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
28 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)
29 GCC_ASM_EXPORT (ArmDrainWriteBuffer)
30 GCC_ASM_EXPORT (ArmEnableMmu)
31 GCC_ASM_EXPORT (ArmDisableMmu)
32 GCC_ASM_EXPORT (ArmDisableCachesAndMmu)
33 GCC_ASM_EXPORT (ArmMmuEnabled)
34 GCC_ASM_EXPORT (ArmEnableDataCache)
35 GCC_ASM_EXPORT (ArmDisableDataCache)
36 GCC_ASM_EXPORT (ArmEnableInstructionCache)
37 GCC_ASM_EXPORT (ArmDisableInstructionCache)
38 GCC_ASM_EXPORT (ArmDisableAlignmentCheck)
39 GCC_ASM_EXPORT (ArmEnableAlignmentCheck)
40 GCC_ASM_EXPORT (ArmEnableBranchPrediction)
41 GCC_ASM_EXPORT (ArmDisableBranchPrediction)
42 GCC_ASM_EXPORT (AArch64AllDataCachesOperation)
43 GCC_ASM_EXPORT (AArch64PerformPoUDataCacheOperation)
44 GCC_ASM_EXPORT (ArmDataMemoryBarrier)
45 GCC_ASM_EXPORT (ArmDataSyncronizationBarrier)
46 GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
47 GCC_ASM_EXPORT (ArmWriteVBar)
48 GCC_ASM_EXPORT (ArmVFPImplemented)
49 GCC_ASM_EXPORT (ArmEnableVFP)
50 GCC_ASM_EXPORT (ArmCallWFI)
51 GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb)
52 GCC_ASM_EXPORT (ArmReadMpidr)
53 GCC_ASM_EXPORT (ArmReadTpidrurw)
54 GCC_ASM_EXPORT (ArmWriteTpidrurw)
55 GCC_ASM_EXPORT (ArmIsArchTimerImplemented)
56 GCC_ASM_EXPORT (ArmReadIdPfr0)
57 GCC_ASM_EXPORT (ArmReadIdPfr1)
58 GCC_ASM_EXPORT (ArmWriteHcr)
59 GCC_ASM_EXPORT (ArmReadCurrentEL)
61 .set CTRL_M_BIT, (1 << 0)
62 .set CTRL_A_BIT, (1 << 1)
63 .set CTRL_C_BIT, (1 << 2)
64 .set CTRL_I_BIT, (1 << 12)
65 .set CTRL_V_BIT, (1 << 12)
66 .set CPACR_VFP_BITS, (3 << 20)
68 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
69 dc ivac, x0 // Invalidate single data cache line
75 ASM_PFX(ArmCleanDataCacheEntryByMVA):
76 dc cvac, x0 // Clean single data cache line
82 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
83 dc civac, x0 // Clean and invalidate single data cache line
89 ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
90 dc isw, x0 // Invalidate this line
96 ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
97 dc cisw, x0 // Clean and Invalidate this line
103 ASM_PFX(ArmCleanDataCacheEntryBySetWay):
104 dc csw, x0 // Clean this line
110 ASM_PFX(ArmInvalidateInstructionCache):
111 ic iallu // Invalidate entire instruction cache
117 ASM_PFX(ArmEnableMmu):
118 EL1_OR_EL2_OR_EL3(x1)
119 1: mrs x0, sctlr_el1 // Read System control register EL1
121 2: mrs x0, sctlr_el2 // Read System control register EL2
123 3: mrs x0, sctlr_el3 // Read System control register EL3
124 4: orr x0, x0, #CTRL_M_BIT // Set MMU enable bit
125 EL1_OR_EL2_OR_EL3(x1)
128 msr sctlr_el1, x0 // Write back
132 msr sctlr_el2, x0 // Write back
136 msr sctlr_el3, x0 // Write back
142 ASM_PFX(ArmDisableMmu):
143 EL1_OR_EL2_OR_EL3(x1)
144 1: mrs x0, sctlr_el1 // Read System Control Register EL1
146 2: mrs x0, sctlr_el2 // Read System Control Register EL2
148 3: mrs x0, sctlr_el3 // Read System Control Register EL3
149 4: bic x0, x0, #CTRL_M_BIT // Clear MMU enable bit
150 EL1_OR_EL2_OR_EL3(x1)
151 1: msr sctlr_el1, x0 // Write back
154 2: msr sctlr_el2, x0 // Write back
157 3: msr sctlr_el3, x0 // Write back
164 ASM_PFX(ArmDisableCachesAndMmu):
165 EL1_OR_EL2_OR_EL3(x1)
166 1: mrs x0, sctlr_el1 // Get control register EL1
168 2: mrs x0, sctlr_el2 // Get control register EL2
170 3: mrs x0, sctlr_el3 // Get control register EL3
171 4: bic x0, x0, #CTRL_M_BIT // Disable MMU
172 bic x0, x0, #CTRL_C_BIT // Disable D Cache
173 bic x0, x0, #CTRL_I_BIT // Disable I Cache
174 EL1_OR_EL2_OR_EL3(x1)
175 1: msr sctlr_el1, x0 // Write back control register
177 2: msr sctlr_el2, x0 // Write back control register
179 3: msr sctlr_el3, x0 // Write back control register
185 ASM_PFX(ArmMmuEnabled):
186 EL1_OR_EL2_OR_EL3(x1)
187 1: mrs x0, sctlr_el1 // Get control register EL1
189 2: mrs x0, sctlr_el2 // Get control register EL2
191 3: mrs x0, sctlr_el3 // Get control register EL3
192 4: and x0, x0, #CTRL_M_BIT
196 ASM_PFX(ArmEnableDataCache):
197 EL1_OR_EL2_OR_EL3(x1)
198 1: mrs x0, sctlr_el1 // Get control register EL1
200 2: mrs x0, sctlr_el2 // Get control register EL2
202 3: mrs x0, sctlr_el3 // Get control register EL3
203 4: orr x0, x0, #CTRL_C_BIT // Set C bit
204 EL1_OR_EL2_OR_EL3(x1)
205 1: msr sctlr_el1, x0 // Write back control register
207 2: msr sctlr_el2, x0 // Write back control register
209 3: msr sctlr_el3, x0 // Write back control register
215 ASM_PFX(ArmDisableDataCache):
216 EL1_OR_EL2_OR_EL3(x1)
217 1: mrs x0, sctlr_el1 // Get control register EL1
219 2: mrs x0, sctlr_el2 // Get control register EL2
221 3: mrs x0, sctlr_el3 // Get control register EL3
222 4: bic x0, x0, #CTRL_C_BIT // Clear C bit
223 EL1_OR_EL2_OR_EL3(x1)
224 1: msr sctlr_el1, x0 // Write back control register
226 2: msr sctlr_el2, x0 // Write back control register
228 3: msr sctlr_el3, x0 // Write back control register
234 ASM_PFX(ArmEnableInstructionCache):
235 EL1_OR_EL2_OR_EL3(x1)
236 1: mrs x0, sctlr_el1 // Get control register EL1
238 2: mrs x0, sctlr_el2 // Get control register EL2
240 3: mrs x0, sctlr_el3 // Get control register EL3
241 4: orr x0, x0, #CTRL_I_BIT // Set I bit
242 EL1_OR_EL2_OR_EL3(x1)
243 1: msr sctlr_el1, x0 // Write back control register
245 2: msr sctlr_el2, x0 // Write back control register
247 3: msr sctlr_el3, x0 // Write back control register
253 ASM_PFX(ArmDisableInstructionCache):
254 EL1_OR_EL2_OR_EL3(x1)
255 1: mrs x0, sctlr_el1 // Get control register EL1
257 2: mrs x0, sctlr_el2 // Get control register EL2
259 3: mrs x0, sctlr_el3 // Get control register EL3
260 4: bic x0, x0, #CTRL_I_BIT // Clear I bit
261 EL1_OR_EL2_OR_EL3(x1)
262 1: msr sctlr_el1, x0 // Write back control register
264 2: msr sctlr_el2, x0 // Write back control register
266 3: msr sctlr_el3, x0 // Write back control register
272 ASM_PFX(ArmEnableAlignmentCheck):
274 1: mrs x0, sctlr_el1 // Get control register EL1
276 2: mrs x0, sctlr_el2 // Get control register EL2
277 3: orr x0, x0, #CTRL_A_BIT // Set A (alignment check) bit
279 1: msr sctlr_el1, x0 // Write back control register
281 2: msr sctlr_el2, x0 // Write back control register
287 ASM_PFX(ArmDisableAlignmentCheck):
288 EL1_OR_EL2_OR_EL3(x1)
289 1: mrs x0, sctlr_el1 // Get control register EL1
291 2: mrs x0, sctlr_el2 // Get control register EL2
293 3: mrs x0, sctlr_el3 // Get control register EL3
294 4: bic x0, x0, #CTRL_A_BIT // Clear A (alignment check) bit
295 EL1_OR_EL2_OR_EL3(x1)
296 1: msr sctlr_el1, x0 // Write back control register
298 2: msr sctlr_el2, x0 // Write back control register
300 3: msr sctlr_el3, x0 // Write back control register
306 // Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now
307 ASM_PFX(ArmEnableBranchPrediction):
311 // Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now.
312 ASM_PFX(ArmDisableBranchPrediction):
316 ASM_PFX(AArch64AllDataCachesOperation):
317 // We can use regs 0-7 and 9-15 without having to save/restore.
318 // Save our link register on the stack.
319 str x30, [sp, #-0x10]!
320 mov x1, x0 // Save Function call in x1
321 mrs x6, clidr_el1 // Read EL1 CLIDR
322 and x3, x6, #0x7000000 // Mask out all but Level of Coherency (LoC)
323 lsr x3, x3, #23 // Left align cache level value
324 cbz x3, L_Finished // No need to clean if LoC is 0
325 mov x10, #0 // Start clean at cache level 0
328 ASM_PFX(AArch64PerformPoUDataCacheOperation):
329 // We can use regs 0-7 and 9-15 without having to save/restore.
330 // Save our link register on the stack.
331 str x30, [sp, #-0x10]!
332 mov x1, x0 // Save Function call in x1
333 mrs x6, clidr_el1 // Read EL1 CLIDR
334 and x3, x6, #0x38000000 // Mask out all but Point of Unification (PoU)
335 lsr x3, x3, #26 // Left align cache level value
336 cbz x3, L_Finished // No need to clean if LoC is 0
337 mov x10, #0 // Start clean at cache level 0
340 add x2, x10, x10, lsr #1 // Work out 3x cachelevel for cache info
341 lsr x12, x6, x2 // bottom 3 bits are the Cache type for this level
342 and x12, x12, #7 // get those 3 bits alone
343 cmp x12, #2 // what cache at this level?
344 b.lt L_Skip // no cache or only instruction cache at this level
345 msr csselr_el1, x10 // write the Cache Size selection register with current level (CSSELR)
346 isb // isb to sync the change to the CacheSizeID reg
347 mrs x12, ccsidr_el1 // reads current Cache Size ID register (CCSIDR)
348 and x2, x12, #0x7 // extract the line length field
349 add x2, x2, #4 // add 4 for the line length offset (log2 16 bytes)
352 and x4, x4, x12, lsr #3 // x4 is the max number on the way size (right aligned)
353 clz w5, w4 // w5 is the bit position of the way size increment
356 and x7, x7, x12, lsr #13 // x7 is the max number of the index size (right aligned)
359 mov x9, x4 // x9 working copy of the max way size (right aligned)
363 orr x0, x10, x11 // factor in the way number and cache number
365 orr x0, x0, x11 // factor in the index number
367 blr x1 // Goto requested cache operation
369 subs x9, x9, #1 // decrement the way number
371 subs x7, x7, #1 // decrement the index
374 add x10, x10, #2 // increment the cache number
385 ASM_PFX(ArmDataMemoryBarrier):
390 ASM_PFX(ArmDataSyncronizationBarrier):
391 ASM_PFX(ArmDrainWriteBuffer):
396 ASM_PFX(ArmInstructionSynchronizationBarrier):
401 ASM_PFX(ArmWriteVBar):
402 EL1_OR_EL2_OR_EL3(x1)
403 1: msr vbar_el1, x0 // Set the Address of the EL1 Vector Table in the VBAR register
405 2: msr vbar_el2, x0 // Set the Address of the EL2 Vector Table in the VBAR register
407 3: msr vbar_el3, x0 // Set the Address of the EL3 Vector Table in the VBAR register
411 ASM_PFX(ArmEnableVFP):
412 // Check whether floating-point is implemented in the processor.
413 mov x1, x30 // Save LR
414 bl ArmReadIdPfr0 // Read EL1 Processor Feature Register (PFR0)
415 mov x30, x1 // Restore LR
416 ands x0, x0, #AARCH64_PFR0_FP// Extract bits indicating VFP implementation
417 cmp x0, #0 // VFP is implemented if '0'.
418 b.ne 4f // Exit if VFP not implemented.
419 // FVP is implemented.
420 // Make sure VFP exceptions are not trapped (to any exception level).
421 mrs x0, cpacr_el1 // Read EL1 Coprocessor Access Control Register (CPACR)
422 orr x0, x0, #CPACR_VFP_BITS // Disable FVP traps to EL1
423 msr cpacr_el1, x0 // Write back EL1 Coprocessor Access Control Register (CPACR)
424 mov x1, #AARCH64_CPTR_TFP // TFP Bit for trapping VFP Exceptions
425 EL1_OR_EL2_OR_EL3(x2)
426 1:ret // Not configurable in EL1
427 2:mrs x0, cptr_el2 // Disable VFP traps to EL2
431 3:mrs x0, cptr_el3 // Disable VFP traps to EL3
442 ASM_PFX(ArmInvalidateInstructionAndDataTlb):
443 EL1_OR_EL2_OR_EL3(x0)
454 ASM_PFX(ArmReadMpidr):
455 mrs x0, mpidr_el1 // read EL1 MPIDR
459 // Keep old function names for C compatibilty for now. Change later?
460 ASM_PFX(ArmReadTpidrurw):
461 mrs x0, tpidr_el0 // read tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)
465 // Keep old function names for C compatibilty for now. Change later?
466 ASM_PFX(ArmWriteTpidrurw):
467 msr tpidr_el0, x0 // write tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)
471 // Arch timers are mandatory on AArch64
472 ASM_PFX(ArmIsArchTimerImplemented):
477 ASM_PFX(ArmReadIdPfr0):
478 mrs x0, id_aa64pfr0_el1 // Read ID_AA64PFR0 Register
482 // Q: id_aa64pfr1_el1 not defined yet. What does this funtion want to access?
483 // A: used to setup arch timer. Check if we have security extensions, permissions to set stuff.
484 // See: ArmPkg/Library/ArmArchTimerLib/AArch64/ArmArchTimerLib.c
485 // Not defined yet, but stick in here for now, should read all zeros.
486 ASM_PFX(ArmReadIdPfr1):
487 mrs x0, id_aa64pfr1_el1 // Read ID_PFR1 Register
490 // VOID ArmWriteHcr(UINTN Hcr)
491 ASM_PFX(ArmWriteHcr):
492 msr hcr_el2, x0 // Write the passed HCR value
495 // UINTN ArmReadCurrentEL(VOID)
496 ASM_PFX(ArmReadCurrentEL):
503 ASM_FUNCTION_REMOVE_IF_UNREFERENCED