ArmPkg/Library/ArmLib/AArch64/AArch64Support.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
   5 #
   6 # This program and the accompanying materials
   7 # are licensed and made available under the terms and conditions of the BSD License
   8 # which accompanies this distribution.  The full text of the license may be found at
   9 # http://opensource.org/licenses/bsd-license.php
  10 #
  11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 #
  14 #------------------------------------------------------------------------------
  15
  16 #include <Chipset/AArch64.h>
  17 #include <AsmMacroIoLibV8.h>
  18
  19 .text
  20 .align 3
  21
  22 GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
  23 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
  24 GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
  25 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
  26 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
  27 GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
  28 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)
  29 GCC_ASM_EXPORT (ArmDrainWriteBuffer)
  30 GCC_ASM_EXPORT (ArmEnableMmu)
  31 GCC_ASM_EXPORT (ArmDisableMmu)
  32 GCC_ASM_EXPORT (ArmDisableCachesAndMmu)
  33 GCC_ASM_EXPORT (ArmMmuEnabled)
  34 GCC_ASM_EXPORT (ArmEnableDataCache)
  35 GCC_ASM_EXPORT (ArmDisableDataCache)
  36 GCC_ASM_EXPORT (ArmEnableInstructionCache)
  37 GCC_ASM_EXPORT (ArmDisableInstructionCache)
  38 GCC_ASM_EXPORT (ArmDisableAlignmentCheck)
  39 GCC_ASM_EXPORT (ArmEnableAlignmentCheck)
  40 GCC_ASM_EXPORT (ArmEnableBranchPrediction)
  41 GCC_ASM_EXPORT (ArmDisableBranchPrediction)
  42 GCC_ASM_EXPORT (AArch64AllDataCachesOperation)
  43 GCC_ASM_EXPORT (AArch64PerformPoUDataCacheOperation)
  44 GCC_ASM_EXPORT (ArmDataMemoryBarrier)
  45 GCC_ASM_EXPORT (ArmDataSyncronizationBarrier)
  46 GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
  47 GCC_ASM_EXPORT (ArmWriteVBar)
  48 GCC_ASM_EXPORT (ArmReadVBar)
  49 GCC_ASM_EXPORT (ArmEnableVFP)
  50 GCC_ASM_EXPORT (ArmCallWFI)
  51 GCC_ASM_EXPORT (ArmReadMpidr)
  52 GCC_ASM_EXPORT (ArmReadTpidrurw)
  53 GCC_ASM_EXPORT (ArmWriteTpidrurw)
  54 GCC_ASM_EXPORT (ArmIsArchTimerImplemented)
  55 GCC_ASM_EXPORT (ArmReadIdPfr0)
  56 GCC_ASM_EXPORT (ArmReadIdPfr1)
  57 GCC_ASM_EXPORT (ArmWriteHcr)
  58 GCC_ASM_EXPORT (ArmReadCurrentEL)
  59
  60 .set CTRL_M_BIT,      (1 << 0)
  61 .set CTRL_A_BIT,      (1 << 1)
  62 .set CTRL_C_BIT,      (1 << 2)
  63 .set CTRL_I_BIT,      (1 << 12)
  64 .set CTRL_V_BIT,      (1 << 12)
  65 .set CPACR_VFP_BITS,  (3 << 20)
  66
  67 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
  68   dc      ivac, x0    // Invalidate single data cache line
  69   dsb     sy
  70   isb
  71   ret
  72
  73
  74 ASM_PFX(ArmCleanDataCacheEntryByMVA):
  75   dc      cvac, x0    // Clean single data cache line
  76   dsb     sy
  77   isb
  78   ret
  79
  80
  81 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
  82   dc      civac, x0   // Clean and invalidate single data cache line
  83   dsb     sy
  84   isb
  85   ret
  86
  87
  88 ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
  89   dc      isw, x0     // Invalidate this line
  90   dsb     sy
  91   isb
  92   ret
  93
  94
  95 ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
  96   dc      cisw, x0    // Clean and Invalidate this line
  97   dsb     sy
  98   isb
  99   ret
 100
 101
 102 ASM_PFX(ArmCleanDataCacheEntryBySetWay):
 103   dc      csw, x0     // Clean this line
 104   dsb     sy
 105   isb
 106   ret
 107
 108
 109 ASM_PFX(ArmInvalidateInstructionCache):
 110   ic      iallu       // Invalidate entire instruction cache
 111   dsb     sy
 112   isb
 113   ret
 114
 115
 116 ASM_PFX(ArmEnableMmu):
 117    EL1_OR_EL2_OR_EL3(x1)
 118 1: mrs     x0, sctlr_el1       // Read System control register EL1
 119    b       4f
 120 2: mrs     x0, sctlr_el2       // Read System control register EL2
 121    b       4f
 122 3: mrs     x0, sctlr_el3       // Read System control register EL3
 123 4: orr     x0, x0, #CTRL_M_BIT // Set MMU enable bit
 124    EL1_OR_EL2_OR_EL3(x1)
 125 1: tlbi    vmalle1
 126    isb
 127    msr     sctlr_el1, x0       // Write back
 128    b       4f
 129 2: tlbi    alle2
 130    isb
 131    msr     sctlr_el2, x0       // Write back
 132    b       4f
 133 3: tlbi    alle3
 134    isb
 135    msr     sctlr_el3, x0       // Write back
 136 4: dsb     sy
 137    isb
 138    ret
 139
 140
 141 ASM_PFX(ArmDisableMmu):
 142    EL1_OR_EL2_OR_EL3(x1)
 143 1: mrs     x0, sctlr_el1        // Read System Control Register EL1
 144    b       4f
 145 2: mrs     x0, sctlr_el2        // Read System Control Register EL2
 146    b       4f
 147 3: mrs     x0, sctlr_el3        // Read System Control Register EL3
 148 4: and     x0, x0, #~CTRL_M_BIT  // Clear MMU enable bit
 149    EL1_OR_EL2_OR_EL3(x1)
 150 1: msr     sctlr_el1, x0        // Write back
 151    tlbi    vmalle1
 152    b       4f
 153 2: msr     sctlr_el2, x0        // Write back
 154    tlbi    alle2
 155    b       4f
 156 3: msr     sctlr_el3, x0        // Write back
 157    tlbi    alle3
 158 4: dsb     sy
 159    isb
 160    ret
 161
 162
 163 ASM_PFX(ArmDisableCachesAndMmu):
 164    EL1_OR_EL2_OR_EL3(x1)
 165 1: mrs     x0, sctlr_el1        // Get control register EL1
 166    b       4f
 167 2: mrs     x0, sctlr_el2        // Get control register EL2
 168    b       4f
 169 3: mrs     x0, sctlr_el3        // Get control register EL3
 170 4: mov     x1, #~(CTRL_M_BIT | CTRL_C_BIT | CTRL_I_BIT)  // Disable MMU, D & I caches
 171    and     x0, x0, x1
 172    EL1_OR_EL2_OR_EL3(x1)
 173 1: msr     sctlr_el1, x0        // Write back control register
 174    b       4f
 175 2: msr     sctlr_el2, x0        // Write back control register
 176    b       4f
 177 3: msr     sctlr_el3, x0        // Write back control register
 178 4: dsb     sy
 179    isb
 180    ret
 181
 182
 183 ASM_PFX(ArmMmuEnabled):
 184    EL1_OR_EL2_OR_EL3(x1)
 185 1: mrs     x0, sctlr_el1        // Get control register EL1
 186    b       4f
 187 2: mrs     x0, sctlr_el2        // Get control register EL2
 188    b       4f
 189 3: mrs     x0, sctlr_el3        // Get control register EL3
 190 4: and     x0, x0, #CTRL_M_BIT
 191    ret
 192
 193
 194 ASM_PFX(ArmEnableDataCache):
 195    EL1_OR_EL2_OR_EL3(x1)
 196 1: mrs     x0, sctlr_el1        // Get control register EL1
 197    b       4f
 198 2: mrs     x0, sctlr_el2        // Get control register EL2
 199    b       4f
 200 3: mrs     x0, sctlr_el3        // Get control register EL3
 201 4: orr     x0, x0, #CTRL_C_BIT  // Set C bit
 202    EL1_OR_EL2_OR_EL3(x1)
 203 1: msr     sctlr_el1, x0        // Write back control register
 204    b       4f
 205 2: msr     sctlr_el2, x0        // Write back control register
 206    b       4f
 207 3: msr     sctlr_el3, x0        // Write back control register
 208 4: dsb     sy
 209    isb
 210    ret
 211
 212
 213 ASM_PFX(ArmDisableDataCache):
 214    EL1_OR_EL2_OR_EL3(x1)
 215 1: mrs     x0, sctlr_el1        // Get control register EL1
 216    b       4f
 217 2: mrs     x0, sctlr_el2        // Get control register EL2
 218    b       4f
 219 3: mrs     x0, sctlr_el3        // Get control register EL3
 220 4: and     x0, x0, #~CTRL_C_BIT  // Clear C bit
 221    EL1_OR_EL2_OR_EL3(x1)
 222 1: msr     sctlr_el1, x0        // Write back control register
 223    b       4f
 224 2: msr     sctlr_el2, x0        // Write back control register
 225    b       4f
 226 3: msr     sctlr_el3, x0        // Write back control register
 227 4: dsb     sy
 228    isb
 229    ret
 230
 231
 232 ASM_PFX(ArmEnableInstructionCache):
 233    EL1_OR_EL2_OR_EL3(x1)
 234 1: mrs     x0, sctlr_el1        // Get control register EL1
 235    b       4f
 236 2: mrs     x0, sctlr_el2        // Get control register EL2
 237    b       4f
 238 3: mrs     x0, sctlr_el3        // Get control register EL3
 239 4: orr     x0, x0, #CTRL_I_BIT  // Set I bit
 240    EL1_OR_EL2_OR_EL3(x1)
 241 1: msr     sctlr_el1, x0        // Write back control register
 242    b       4f
 243 2: msr     sctlr_el2, x0        // Write back control register
 244    b       4f
 245 3: msr     sctlr_el3, x0        // Write back control register
 246 4: dsb     sy
 247    isb
 248    ret
 249
 250
 251 ASM_PFX(ArmDisableInstructionCache):
 252    EL1_OR_EL2_OR_EL3(x1)
 253 1: mrs     x0, sctlr_el1        // Get control register EL1
 254    b       4f
 255 2: mrs     x0, sctlr_el2        // Get control register EL2
 256    b       4f
 257 3: mrs     x0, sctlr_el3        // Get control register EL3
 258 4: and     x0, x0, #~CTRL_I_BIT  // Clear I bit
 259    EL1_OR_EL2_OR_EL3(x1)
 260 1: msr     sctlr_el1, x0        // Write back control register
 261    b       4f
 262 2: msr     sctlr_el2, x0        // Write back control register
 263    b       4f
 264 3: msr     sctlr_el3, x0        // Write back control register
 265 4: dsb     sy
 266    isb
 267    ret
 268
 269
 270 ASM_PFX(ArmEnableAlignmentCheck):
 271    EL1_OR_EL2(x1)
 272 1: mrs     x0, sctlr_el1        // Get control register EL1
 273    b       3f
 274 2: mrs     x0, sctlr_el2        // Get control register EL2
 275 3: orr     x0, x0, #CTRL_A_BIT  // Set A (alignment check) bit
 276    EL1_OR_EL2(x1)
 277 1: msr     sctlr_el1, x0        // Write back control register
 278    b       3f
 279 2: msr     sctlr_el2, x0        // Write back control register
 280 3: dsb     sy
 281    isb
 282    ret
 283
 284
 285 ASM_PFX(ArmDisableAlignmentCheck):
 286    EL1_OR_EL2_OR_EL3(x1)
 287 1: mrs     x0, sctlr_el1        // Get control register EL1
 288    b       4f
 289 2: mrs     x0, sctlr_el2        // Get control register EL2
 290    b       4f
 291 3: mrs     x0, sctlr_el3        // Get control register EL3
 292 4: and     x0, x0, #~CTRL_A_BIT  // Clear A (alignment check) bit
 293    EL1_OR_EL2_OR_EL3(x1)
 294 1: msr     sctlr_el1, x0        // Write back control register
 295    b       4f
 296 2: msr     sctlr_el2, x0        // Write back control register
 297    b       4f
 298 3: msr     sctlr_el3, x0        // Write back control register
 299 4: dsb     sy
 300    isb
 301    ret
 302
 303
 304 // Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now
 305 ASM_PFX(ArmEnableBranchPrediction):
 306   ret
 307
 308
 309 // Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now.
 310 ASM_PFX(ArmDisableBranchPrediction):
 311   ret
 312
 313
 314 ASM_PFX(AArch64AllDataCachesOperation):
 315 // We can use regs 0-7 and 9-15 without having to save/restore.
 316 // Save our link register on the stack. - The stack must always be quad-word aligned
 317   str   x30, [sp, #-16]!
 318   mov   x1, x0                  // Save Function call in x1
 319   mrs   x6, clidr_el1           // Read EL1 CLIDR
 320   and   x3, x6, #0x7000000      // Mask out all but Level of Coherency (LoC)
 321   lsr   x3, x3, #23             // Left align cache level value - the level is shifted by 1 to the
 322                                 // right to ease the access to CSSELR and the Set/Way operation.
 323   cbz   x3, L_Finished          // No need to clean if LoC is 0
 324   mov   x10, #0                 // Start clean at cache level 0
 325   b     Loop1
 326
 327 ASM_PFX(AArch64PerformPoUDataCacheOperation):
 328 // We can use regs 0-7 and 9-15 without having to save/restore.
 329 // Save our link register on the stack. - The stack must always be quad-word aligned
 330   str   x30, [sp, #-16]!
 331   mov   x1, x0                  // Save Function call in x1
 332   mrs   x6, clidr_el1           // Read EL1 CLIDR
 333   and   x3, x6, #0x38000000     // Mask out all but Point of Unification (PoU)
 334   lsr   x3, x3, #26             // Left align cache level value - the level is shifted by 1 to the
 335                                 // right to ease the access to CSSELR and the Set/Way operation.
 336   cbz   x3, L_Finished          // No need to clean if LoC is 0
 337   mov   x10, #0                 // Start clean at cache level 0
 338
 339 Loop1:
 340   add   x2, x10, x10, lsr #1    // Work out 3x cachelevel for cache info
 341   lsr   x12, x6, x2             // bottom 3 bits are the Cache type for this level
 342   and   x12, x12, #7            // get those 3 bits alone
 343   cmp   x12, #2                 // what cache at this level?
 344   b.lt  L_Skip                  // no cache or only instruction cache at this level
 345   msr   csselr_el1, x10         // write the Cache Size selection register with current level (CSSELR)
 346   isb                           // isb to sync the change to the CacheSizeID reg
 347   mrs   x12, ccsidr_el1         // reads current Cache Size ID register (CCSIDR)
 348   and   x2, x12, #0x7           // extract the line length field
 349   add   x2, x2, #4              // add 4 for the line length offset (log2 16 bytes)
 350   mov   x4, #0x400
 351   sub   x4, x4, #1
 352   and   x4, x4, x12, lsr #3     // x4 is the max number on the way size (right aligned)
 353   clz   w5, w4                  // w5 is the bit position of the way size increment
 354   mov   x7, #0x00008000
 355   sub   x7, x7, #1
 356   and   x7, x7, x12, lsr #13    // x7 is the max number of the index size (right aligned)
 357
 358 Loop2:
 359   mov   x9, x4                  // x9 working copy of the max way size (right aligned)
 360
 361 Loop3:
 362   lsl   x11, x9, x5
 363   orr   x0, x10, x11            // factor in the way number and cache number
 364   lsl   x11, x7, x2
 365   orr   x0, x0, x11             // factor in the index number
 366
 367   blr   x1                      // Goto requested cache operation
 368
 369   subs  x9, x9, #1              // decrement the way number
 370   b.ge  Loop3
 371   subs  x7, x7, #1              // decrement the index
 372   b.ge  Loop2
 373 L_Skip:
 374   add   x10, x10, #2            // increment the cache number
 375   cmp   x3, x10
 376   b.gt  Loop1
 377
 378 L_Finished:
 379   dsb   sy
 380   isb
 381   ldr   x30, [sp], #0x10
 382   ret
 383
 384
 385 ASM_PFX(ArmDataMemoryBarrier):
 386   dmb   sy
 387   ret
 388
 389
 390 ASM_PFX(ArmDataSyncronizationBarrier):
 391 ASM_PFX(ArmDrainWriteBuffer):
 392   dsb   sy
 393   ret
 394
 395
 396 ASM_PFX(ArmInstructionSynchronizationBarrier):
 397   isb
 398   ret
 399
 400
 401 ASM_PFX(ArmWriteVBar):
 402    EL1_OR_EL2_OR_EL3(x1)
 403 1: msr   vbar_el1, x0            // Set the Address of the EL1 Vector Table in the VBAR register
 404    b     4f
 405 2: msr   vbar_el2, x0            // Set the Address of the EL2 Vector Table in the VBAR register
 406    b     4f
 407 3: msr   vbar_el3, x0            // Set the Address of the EL3 Vector Table in the VBAR register
 408 4: isb
 409    ret
 410
 411 ASM_PFX(ArmReadVBar):
 412    EL1_OR_EL2_OR_EL3(x1)
 413 1: mrs   x0, vbar_el1            // Set the Address of the EL1 Vector Table in the VBAR register
 414    ret
 415 2: mrs   x0, vbar_el2            // Set the Address of the EL2 Vector Table in the VBAR register
 416    ret
 417 3: mrs   x0, vbar_el3            // Set the Address of the EL3 Vector Table in the VBAR register
 418    ret
 419
 420
 421 ASM_PFX(ArmEnableVFP):
 422   // Check whether floating-point is implemented in the processor.
 423   mov   x1, x30                 // Save LR
 424   bl    ArmReadIdPfr0           // Read EL1 Processor Feature Register (PFR0)
 425   mov   x30, x1                 // Restore LR
 426   ands  x0, x0, #AARCH64_PFR0_FP// Extract bits indicating VFP implementation
 427   cmp   x0, #0                  // VFP is implemented if '0'.
 428   b.ne  4f                      // Exit if VFP not implemented.
 429   // FVP is implemented.
 430   // Make sure VFP exceptions are not trapped (to any exception level).
 431   mrs   x0, cpacr_el1           // Read EL1 Coprocessor Access Control Register (CPACR)
 432   orr   x0, x0, #CPACR_VFP_BITS // Disable FVP traps to EL1
 433   msr   cpacr_el1, x0           // Write back EL1 Coprocessor Access Control Register (CPACR)
 434   mov   x1, #AARCH64_CPTR_TFP   // TFP Bit for trapping VFP Exceptions
 435   EL1_OR_EL2_OR_EL3(x2)
 436 1:ret                           // Not configurable in EL1
 437 2:mrs   x0, cptr_el2            // Disable VFP traps to EL2
 438   bic   x0, x0, x1
 439   msr   cptr_el2, x0
 440   ret
 441 3:mrs   x0, cptr_el3            // Disable VFP traps to EL3
 442   bic   x0, x0, x1
 443   msr   cptr_el3, x0
 444 4:ret
 445
 446
 447 ASM_PFX(ArmCallWFI):
 448   wfi
 449   ret
 450
 451
 452 ASM_PFX(ArmReadMpidr):
 453   mrs   x0, mpidr_el1           // read EL1 MPIDR
 454   ret
 455
 456
 457 // Keep old function names for C compatibilty for now. Change later?
 458 ASM_PFX(ArmReadTpidrurw):
 459   mrs   x0, tpidr_el0           // read tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)
 460   ret
 461
 462
 463 // Keep old function names for C compatibilty for now. Change later?
 464 ASM_PFX(ArmWriteTpidrurw):
 465   msr   tpidr_el0, x0           // write tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)
 466   ret
 467
 468
 469 // Arch timers are mandatory on AArch64
 470 ASM_PFX(ArmIsArchTimerImplemented):
 471   mov   x0, #1
 472   ret
 473
 474
 475 ASM_PFX(ArmReadIdPfr0):
 476   mrs   x0, id_aa64pfr0_el1   // Read ID_AA64PFR0 Register
 477   ret
 478
 479
 480 // Q: id_aa64pfr1_el1 not defined yet. What does this funtion want to access?
 481 // A: used to setup arch timer. Check if we have security extensions, permissions to set stuff.
 482 //    See: ArmPkg/Library/ArmArchTimerLib/AArch64/ArmArchTimerLib.c
 483 //    Not defined yet, but stick in here for now, should read all zeros.
 484 ASM_PFX(ArmReadIdPfr1):
 485   mrs   x0, id_aa64pfr1_el1   // Read ID_PFR1 Register
 486   ret
 487
 488 // VOID ArmWriteHcr(UINTN Hcr)
 489 ASM_PFX(ArmWriteHcr):
 490   msr   hcr_el2, x0        // Write the passed HCR value
 491   ret
 492
 493 // UINTN ArmReadCurrentEL(VOID)
 494 ASM_PFX(ArmReadCurrentEL):
 495   mrs   x0, CurrentEL
 496   ret
 497
 498 ASM_FUNCTION_REMOVE_IF_UNREFERENCED