ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.
   5 # Copyright (c) 2016, Linaro Limited. All rights reserved.
   6 #
   7 # SPDX-License-Identifier: BSD-2-Clause-Patent
   8 #
   9 #------------------------------------------------------------------------------
  10
  11 #include <AsmMacroIoLibV8.h>
  12
  13 .set DAIF_RD_FIQ_BIT,   (1 << 6)
  14 .set DAIF_RD_IRQ_BIT,   (1 << 7)
  15
  16 .set SCTLR_ELx_M_BIT_POS, (0)
  17
  18 ASM_FUNC(ArmReadMidr)
  19   mrs     x0, midr_el1        // Read from Main ID Register (MIDR)
  20   ret
  21
  22 ASM_FUNC(ArmCacheInfo)
  23   mrs     x0, ctr_el0         // Read from Cache Type Regiter (CTR)
  24   ret
  25
  26 ASM_FUNC(ArmGetInterruptState)
  27   mrs     x0, daif
  28   tst     w0, #DAIF_RD_IRQ_BIT  // Check if IRQ is enabled. Enabled if 0 (Z=1)
  29   cset    w0, eq                // if Z=1 return 1, else 0
  30   ret
  31
  32 ASM_FUNC(ArmGetFiqState)
  33   mrs     x0, daif
  34   tst     w0, #DAIF_RD_FIQ_BIT  // Check if FIQ is enabled. Enabled if 0 (Z=1)
  35   cset    w0, eq                // if Z=1 return 1, else 0
  36   ret
  37
  38 ASM_FUNC(ArmWriteCpacr)
  39   msr     cpacr_el1, x0      // Coprocessor Access Control Reg (CPACR)
  40   ret
  41
  42 ASM_FUNC(ArmWriteAuxCr)
  43   EL1_OR_EL2(x1)
  44 1:msr     actlr_el1, x0      // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
  45   ret
  46 2:msr     actlr_el2, x0      // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
  47   ret
  48
  49 ASM_FUNC(ArmReadAuxCr)
  50   EL1_OR_EL2(x1)
  51 1:mrs     x0, actlr_el1      // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
  52   ret
  53 2:mrs     x0, actlr_el2      // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
  54   ret
  55
  56 ASM_FUNC(ArmSetTTBR0)
  57   EL1_OR_EL2_OR_EL3(x1)
  58 1:msr     ttbr0_el1, x0      // Translation Table Base Reg 0 (TTBR0)
  59   b       4f
  60 2:msr     ttbr0_el2, x0      // Translation Table Base Reg 0 (TTBR0)
  61   b       4f
  62 3:msr     ttbr0_el3, x0      // Translation Table Base Reg 0 (TTBR0)
  63 4:isb
  64   ret
  65
  66 ASM_FUNC(ArmGetTTBR0BaseAddress)
  67   EL1_OR_EL2(x1)
  68 1:mrs     x0, ttbr0_el1
  69   b       3f
  70 2:mrs     x0, ttbr0_el2
  71 3:and     x0, x0, 0xFFFFFFFFFFFF  /* Look at bottom 48 bits */
  72   isb
  73   ret
  74
  75 ASM_FUNC(ArmGetTCR)
  76   EL1_OR_EL2_OR_EL3(x1)
  77 1:mrs     x0, tcr_el1
  78   b       4f
  79 2:mrs     x0, tcr_el2
  80   b       4f
  81 3:mrs     x0, tcr_el3
  82 4:isb
  83   ret
  84
  85 ASM_FUNC(ArmSetTCR)
  86   EL1_OR_EL2_OR_EL3(x1)
  87 1:msr     tcr_el1, x0
  88   b       4f
  89 2:msr     tcr_el2, x0
  90   b       4f
  91 3:msr     tcr_el3, x0
  92 4:isb
  93   ret
  94
  95 ASM_FUNC(ArmGetMAIR)
  96   EL1_OR_EL2_OR_EL3(x1)
  97 1:mrs     x0, mair_el1
  98   b       4f
  99 2:mrs     x0, mair_el2
 100   b       4f
 101 3:mrs     x0, mair_el3
 102 4:isb
 103   ret
 104
 105 ASM_FUNC(ArmSetMAIR)
 106   EL1_OR_EL2_OR_EL3(x1)
 107 1:msr     mair_el1, x0
 108   b       4f
 109 2:msr     mair_el2, x0
 110   b       4f
 111 3:msr     mair_el3, x0
 112 4:isb
 113   ret
 114
 115
 116 //
 117 //VOID
 118 //ArmUpdateTranslationTableEntry (
 119 //  IN VOID  *TranslationTableEntry  // X0
 120 //  IN VOID  *MVA                    // X1
 121 //  );
 122 ASM_FUNC(ArmUpdateTranslationTableEntry)
 123    dsb     nshst
 124    lsr     x1, x1, #12
 125    EL1_OR_EL2_OR_EL3(x0)
 126 1: tlbi    vaae1, x1             // TLB Invalidate VA , EL1
 127    mrs     x2, sctlr_el1
 128    b       4f
 129 2: tlbi    vae2, x1              // TLB Invalidate VA , EL2
 130    mrs     x2, sctlr_el2
 131    b       4f
 132 3: tlbi    vae3, x1              // TLB Invalidate VA , EL3
 133    mrs     x2, sctlr_el3
 134 4: tbnz    x2, SCTLR_ELx_M_BIT_POS, 5f
 135    dc      ivac, x0              // invalidate in Dcache if MMU is still off
 136 5: dsb     nsh
 137    isb
 138    ret
 139
 140 ASM_FUNC(ArmInvalidateTlb)
 141    EL1_OR_EL2_OR_EL3(x0)
 142 1: tlbi  vmalle1
 143    b     4f
 144 2: tlbi  alle2
 145    b     4f
 146 3: tlbi  alle3
 147 4: dsb   sy
 148    isb
 149    ret
 150
 151 ASM_FUNC(ArmWriteCptr)
 152   msr     cptr_el3, x0           // EL3 Coprocessor Trap Reg (CPTR)
 153   ret
 154
 155 ASM_FUNC(ArmWriteScr)
 156   msr     scr_el3, x0            // Secure configuration register EL3
 157   isb
 158   ret
 159
 160 ASM_FUNC(ArmWriteMVBar)
 161   msr    vbar_el3, x0            // Exception Vector Base address for Monitor on EL3
 162   ret
 163
 164 ASM_FUNC(ArmCallWFE)
 165   wfe
 166   ret
 167
 168 ASM_FUNC(ArmCallSEV)
 169   sev
 170   ret
 171
 172 ASM_FUNC(ArmReadCpuActlr)
 173   mrs   x0, S3_1_c15_c2_0
 174   ret
 175
 176 ASM_FUNC(ArmWriteCpuActlr)
 177   msr   S3_1_c15_c2_0, x0
 178   dsb   sy
 179   isb
 180   ret
 181
 182 ASM_FUNC(ArmReadSctlr)
 183   EL1_OR_EL2_OR_EL3(x1)
 184 1:mrs   x0, sctlr_el1
 185   ret
 186 2:mrs   x0, sctlr_el2
 187   ret
 188 3:mrs   x0, sctlr_el3
 189 4:ret
 190
 191 ASM_FUNC(ArmWriteSctlr)
 192   EL1_OR_EL2_OR_EL3(x1)
 193 1:msr   sctlr_el1, x0
 194   ret
 195 2:msr   sctlr_el2, x0
 196   ret
 197 3:msr   sctlr_el3, x0
 198 4:ret
 199
 200 ASM_FUNC(ArmGetPhysicalAddressBits)
 201   mrs   x0, id_aa64mmfr0_el1
 202   adr   x1, .LPARanges
 203   and   x0, x0, #0xf
 204   ldrb  w0, [x1, x0]
 205   ret
 206
 207 //
 208 // Bits 0..3 of the AA64MFR0_EL1 system register encode the size of the
 209 // physical address space support on this CPU:
 210 // 0 == 32 bits, 1 == 36 bits, etc etc
 211 // 7 and up are reserved
 212 //
 213 .LPARanges:
 214   .byte 32, 36, 40, 42, 44, 48, 52,  0
 215   .byte  0,  0,  0,  0,  0,  0,  0,  0
 216
 217 ASM_FUNCTION_REMOVE_IF_UNREFERENCED