ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
   5 # Copyright (c) 2016, Linaro Limited. All rights reserved.
   6 #
   7 # SPDX-License-Identifier: BSD-2-Clause-Patent
   8 #
   9 #------------------------------------------------------------------------------
  10
  11 #include <AsmMacroIoLibV8.h>
  12
  13 .set MPIDR_U_BIT,    (30)
  14 .set MPIDR_U_MASK,   (1 << MPIDR_U_BIT)
  15
  16 // DAIF bit definitions for writing through msr daifclr/sr daifset
  17 .set DAIF_WR_FIQ_BIT,   (1 << 0)
  18 .set DAIF_WR_IRQ_BIT,   (1 << 1)
  19 .set DAIF_WR_ABORT_BIT, (1 << 2)
  20 .set DAIF_WR_DEBUG_BIT, (1 << 3)
  21 .set DAIF_WR_INT_BITS,  (DAIF_WR_FIQ_BIT | DAIF_WR_IRQ_BIT)
  22 .set DAIF_WR_ALL,       (DAIF_WR_DEBUG_BIT | DAIF_WR_ABORT_BIT | DAIF_WR_INT_BITS)
  23
  24
  25 ASM_FUNC(ArmIsMpCore)
  26   mrs   x0, mpidr_el1         // Read EL1 Multiprocessor Affinty Reg (MPIDR)
  27   and   x0, x0, #MPIDR_U_MASK // U Bit clear, the processor is part of a multiprocessor system
  28   lsr   x0, x0, #MPIDR_U_BIT
  29   eor   x0, x0, #1
  30   ret
  31
  32
  33 ASM_FUNC(ArmEnableAsynchronousAbort)
  34   msr   daifclr, #DAIF_WR_ABORT_BIT
  35   isb
  36   ret
  37
  38
  39 ASM_FUNC(ArmDisableAsynchronousAbort)
  40   msr   daifset, #DAIF_WR_ABORT_BIT
  41   isb
  42   ret
  43
  44
  45 ASM_FUNC(ArmEnableIrq)
  46   msr   daifclr, #DAIF_WR_IRQ_BIT
  47   isb
  48   ret
  49
  50
  51 ASM_FUNC(ArmDisableIrq)
  52   msr   daifset, #DAIF_WR_IRQ_BIT
  53   isb
  54   ret
  55
  56
  57 ASM_FUNC(ArmEnableFiq)
  58   msr   daifclr, #DAIF_WR_FIQ_BIT
  59   isb
  60   ret
  61
  62
  63 ASM_FUNC(ArmDisableFiq)
  64   msr   daifset, #DAIF_WR_FIQ_BIT
  65   isb
  66   ret
  67
  68
  69 ASM_FUNC(ArmEnableInterrupts)
  70   msr   daifclr, #DAIF_WR_INT_BITS
  71   isb
  72   ret
  73
  74
  75 ASM_FUNC(ArmDisableInterrupts)
  76   msr   daifset, #DAIF_WR_INT_BITS
  77   isb
  78   ret
  79
  80
  81 ASM_FUNC(ArmDisableAllExceptions)
  82   msr   daifset, #DAIF_WR_ALL
  83   isb
  84   ret
  85
  86
  87 // UINTN
  88 // ReadCCSIDR (
  89 //   IN UINT32 CSSELR
  90 //   )
  91 ASM_FUNC(ReadCCSIDR)
  92   msr   csselr_el1, x0        // Write Cache Size Selection Register (CSSELR)
  93   isb
  94   mrs   x0, ccsidr_el1        // Read current Cache Size ID Register (CCSIDR)
  95   ret
  96
  97
  98 // UINT32
  99 // ReadCLIDR (
 100 //   IN UINT32 CSSELR
 101 //   )
 102 ASM_FUNC(ReadCLIDR)
 103   mrs   x0, clidr_el1         // Read Cache Level ID Register
 104   ret
 105
 106 ASM_FUNCTION_REMOVE_IF_UNREFERENCED