ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.
   5 # Copyright (c) 2016, Linaro Limited. All rights reserved.
   6 #
   7 # SPDX-License-Identifier: BSD-2-Clause-Patent
   8 #
   9 #------------------------------------------------------------------------------
  10
  11 #include <AsmMacroIoLib.h>
  12
  13 ASM_FUNC(ArmReadMidr)
  14   mrc     p15,0,R0,c0,c0,0
  15   bx      LR
  16
  17 ASM_FUNC(ArmCacheInfo)
  18   mrc     p15,0,R0,c0,c0,1
  19   bx      LR
  20
  21 ASM_FUNC(ArmGetInterruptState)
  22   mrs     R0,CPSR
  23   tst     R0,#0x80      @Check if IRQ is enabled.
  24   moveq   R0,#1
  25   movne   R0,#0
  26   bx      LR
  27
  28 ASM_FUNC(ArmGetFiqState)
  29   mrs     R0,CPSR
  30   tst     R0,#0x40      @Check if FIQ is enabled.
  31   moveq   R0,#1
  32   movne   R0,#0
  33   bx      LR
  34
  35 ASM_FUNC(ArmSetDomainAccessControl)
  36   mcr     p15,0,r0,c3,c0,0
  37   bx      lr
  38
  39 ASM_FUNC(CPSRMaskInsert)    @ on entry, r0 is the mask and r1 is the field to insert
  40   stmfd   sp!, {r4-r12, lr} @ save all the banked registers
  41   mov     r3, sp            @ copy the stack pointer into a non-banked register
  42   mrs     r2, cpsr          @ read the cpsr
  43   bic     r2, r2, r0        @ clear mask in the cpsr
  44   and     r1, r1, r0        @ clear bits outside the mask in the input
  45   orr     r2, r2, r1        @ set field
  46   msr     cpsr_cxsf, r2     @ write back cpsr (may have caused a mode switch)
  47   isb
  48   mov     sp, r3            @ restore stack pointer
  49   ldmfd   sp!, {r4-r12, lr} @ restore registers
  50   bx      lr                @ return (hopefully thumb-safe!)
  51
  52 ASM_FUNC(CPSRRead)
  53   mrs     r0, cpsr
  54   bx      lr
  55
  56 ASM_FUNC(ArmReadCpacr)
  57   mrc     p15, 0, r0, c1, c0, 2
  58   bx      lr
  59
  60 ASM_FUNC(ArmWriteCpacr)
  61   mcr     p15, 0, r0, c1, c0, 2
  62   isb
  63   bx      lr
  64
  65 ASM_FUNC(ArmWriteAuxCr)
  66   mcr     p15, 0, r0, c1, c0, 1
  67   bx      lr
  68
  69 ASM_FUNC(ArmReadAuxCr)
  70   mrc     p15, 0, r0, c1, c0, 1
  71   bx      lr
  72
  73 ASM_FUNC(ArmSetTTBR0)
  74   mcr     p15,0,r0,c2,c0,0
  75   isb
  76   bx      lr
  77
  78 ASM_FUNC(ArmSetTTBCR)
  79   mcr     p15, 0, r0, c2, c0, 2
  80   isb
  81   bx      lr
  82
  83 ASM_FUNC(ArmGetTTBR0BaseAddress)
  84   mrc     p15,0,r0,c2,c0,0
  85   MOV32   (r1, 0xFFFFC000)
  86   and     r0, r0, r1
  87   isb
  88   bx      lr
  89
  90 //
  91 //VOID
  92 //ArmUpdateTranslationTableEntry (
  93 //  IN VOID  *TranslationTableEntry  // R0
  94 //  IN VOID  *MVA                    // R1
  95 //  );
  96 ASM_FUNC(ArmUpdateTranslationTableEntry)
  97   mcr     p15,0,R1,c8,c7,1      @ TLBIMVA TLB Invalidate MVA
  98   mcr     p15,0,R9,c7,c5,6      @ BPIALL Invalidate Branch predictor array. R9 == NoOp
  99   dsb
 100   isb
 101   bx      lr
 102
 103 ASM_FUNC(ArmInvalidateTlb)
 104   mov     r0,#0
 105   mcr     p15,0,r0,c8,c7,0
 106   mcr     p15,0,R9,c7,c5,6      @ BPIALL Invalidate Branch predictor array. R9 == NoOp
 107   dsb
 108   isb
 109   bx      lr
 110
 111 ASM_FUNC(ArmReadScr)
 112   mrc     p15, 0, r0, c1, c1, 0
 113   bx      lr
 114
 115 ASM_FUNC(ArmWriteScr)
 116   mcr     p15, 0, r0, c1, c1, 0
 117   isb
 118   bx      lr
 119
 120 ASM_FUNC(ArmReadHVBar)
 121   mrc     p15, 4, r0, c12, c0, 0
 122   bx      lr
 123
 124 ASM_FUNC(ArmWriteHVBar)
 125   mcr     p15, 4, r0, c12, c0, 0
 126   bx      lr
 127
 128 ASM_FUNC(ArmReadMVBar)
 129   mrc     p15, 0, r0, c12, c0, 1
 130   bx      lr
 131
 132 ASM_FUNC(ArmWriteMVBar)
 133   mcr     p15, 0, r0, c12, c0, 1
 134   bx      lr
 135
 136 ASM_FUNC(ArmCallWFE)
 137   wfe
 138   bx      lr
 139
 140 ASM_FUNC(ArmCallSEV)
 141   sev
 142   bx      lr
 143
 144 ASM_FUNC(ArmReadSctlr)
 145   mrc     p15, 0, r0, c1, c0, 0      @ Read SCTLR into R0 (Read control register configuration data)
 146   bx      lr
 147
 148 ASM_FUNC(ArmWriteSctlr)
 149   mcr     p15, 0, r0, c1, c0, 0
 150   bx      lr
 151
 152 ASM_FUNC(ArmReadCpuActlr)
 153   mrc     p15, 0, r0, c1, c0, 1
 154   bx      lr
 155
 156 ASM_FUNC(ArmWriteCpuActlr)
 157   mcr     p15, 0, r0, c1, c0, 1
 158   dsb
 159   isb
 160   bx      lr
 161
 162 ASM_FUNC (ArmGetPhysicalAddressBits)
 163   mrc     p15, 0, r0, c0, c1, 4   // MMFR0
 164   and     r0, r0, #0xf            // VMSA [3:0]
 165   cmp     r0, #5                  // >= 5 implies LPAE support
 166   movlt   r0, #32                 // 32 bits if no LPAE
 167   movge   r0, #40                 // 40 bits if LPAE
 168   bx      lr
 169
 170 ASM_FUNCTION_REMOVE_IF_UNREFERENCED