ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
   4 // Copyright (c) 2011-2013, ARM Limited. All rights reserved.
   5 //
   6 // SPDX-License-Identifier: BSD-2-Clause-Patent
   7 //
   8 //------------------------------------------------------------------------------
   9
  10
  11
  12     INCLUDE AsmMacroExport.inc
  13
  14
  15 //------------------------------------------------------------------------------
  16
  17  RVCT_ASM_EXPORT ArmIsMpCore
  18   mrc     p15,0,R0,c0,c0,5
  19   // Get Multiprocessing extension (bit31) & U bit (bit30)
  20   and     R0, R0, #0xC0000000
  21   // if (bit31 == 1) && (bit30 == 0) then the processor is part of a multiprocessor system
  22   cmp     R0, #0x80000000
  23   moveq   R0, #1
  24   movne   R0, #0
  25   bx      LR
  26
  27  RVCT_ASM_EXPORT ArmEnableAsynchronousAbort
  28   cpsie   a
  29   isb
  30   bx      LR
  31
  32  RVCT_ASM_EXPORT ArmDisableAsynchronousAbort
  33   cpsid   a
  34   isb
  35   bx      LR
  36
  37  RVCT_ASM_EXPORT ArmEnableIrq
  38   cpsie   i
  39   isb
  40   bx      LR
  41
  42  RVCT_ASM_EXPORT ArmDisableIrq
  43   cpsid   i
  44   isb
  45   bx      LR
  46
  47  RVCT_ASM_EXPORT ArmEnableFiq
  48   cpsie   f
  49   isb
  50   bx      LR
  51
  52  RVCT_ASM_EXPORT ArmDisableFiq
  53   cpsid   f
  54   isb
  55   bx      LR
  56
  57  RVCT_ASM_EXPORT ArmEnableInterrupts
  58   cpsie   if
  59   isb
  60   bx      LR
  61
  62  RVCT_ASM_EXPORT ArmDisableInterrupts
  63   cpsid   if
  64   isb
  65   bx      LR
  66
  67 // UINT32
  68 // ReadCCSIDR (
  69 //   IN UINT32 CSSELR
  70 //   )
  71  RVCT_ASM_EXPORT ReadCCSIDR
  72   mcr p15,2,r0,c0,c0,0   ; Write Cache Size Selection Register (CSSELR)
  73   isb
  74   mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
  75   bx  lr
  76
  77 // UINT32
  78 // ReadCLIDR (
  79 //   IN UINT32 CSSELR
  80 //   )
  81  RVCT_ASM_EXPORT ReadCLIDR
  82   mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
  83   bx  lr
  84
  85  RVCT_ASM_EXPORT ArmReadNsacr
  86   mrc     p15, 0, r0, c1, c1, 2
  87   bx      lr
  88
  89  RVCT_ASM_EXPORT ArmWriteNsacr
  90   mcr     p15, 0, r0, c1, c1, 2
  91   bx      lr
  92
  93   END