ArmPkg/Library/ArmLib/Arm/ArmV7Support.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
   5 # Copyright (c) 2016, Linaro Limited. All rights reserved.
   6 #
   7 # SPDX-License-Identifier: BSD-2-Clause-Patent
   8 #
   9 #------------------------------------------------------------------------------
  10
  11 #include <AsmMacroIoLib.h>
  12
  13 .set DC_ON, (0x1<<2)
  14 .set IC_ON, (0x1<<12)
  15 .set CTRL_M_BIT,  (1 << 0)
  16 .set CTRL_C_BIT,  (1 << 2)
  17 .set CTRL_B_BIT,  (1 << 7)
  18 .set CTRL_I_BIT,  (1 << 12)
  19
  20
  21 ASM_FUNC(ArmInvalidateDataCacheEntryByMVA)
  22   mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line
  23   bx      lr
  24
  25 ASM_FUNC(ArmCleanDataCacheEntryByMVA)
  26   mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line
  27   bx      lr
  28
  29
  30 ASM_FUNC(ArmCleanDataCacheEntryToPoUByMVA)
  31   mcr     p15, 0, r0, c7, c11, 1  @clean single data cache line to PoU
  32   bx      lr
  33
  34 ASM_FUNC(ArmInvalidateInstructionCacheEntryToPoUByMVA)
  35   mcr     p15, 0, r0, c7, c5, 1  @Invalidate single instruction cache line to PoU
  36   mcr     p15, 0, r0, c7, c5, 7  @Invalidate branch predictor
  37   bx      lr
  38
  39 ASM_FUNC(ArmCleanInvalidateDataCacheEntryByMVA)
  40   mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line
  41   bx      lr
  42
  43
  44 ASM_FUNC(ArmInvalidateDataCacheEntryBySetWay)
  45   mcr     p15, 0, r0, c7, c6, 2        @ Invalidate this line
  46   bx      lr
  47
  48
  49 ASM_FUNC(ArmCleanInvalidateDataCacheEntryBySetWay)
  50   mcr     p15, 0, r0, c7, c14, 2       @ Clean and Invalidate this line
  51   bx      lr
  52
  53
  54 ASM_FUNC(ArmCleanDataCacheEntryBySetWay)
  55   mcr     p15, 0, r0, c7, c10, 2       @ Clean this line
  56   bx      lr
  57
  58 ASM_FUNC(ArmInvalidateInstructionCache)
  59   mcr     p15,0,R0,c7,c5,0      @Invalidate entire instruction cache
  60   dsb
  61   isb
  62   bx      LR
  63
  64 ASM_FUNC(ArmEnableMmu)
  65   mrc     p15,0,R0,c1,c0,0
  66   orr     R0,R0,#1
  67   mcr     p15,0,R0,c1,c0,0
  68   dsb
  69   isb
  70   bx      LR
  71
  72
  73 ASM_FUNC(ArmDisableMmu)
  74   mrc     p15,0,R0,c1,c0,0
  75   bic     R0,R0,#1
  76   mcr     p15,0,R0,c1,c0,0      @Disable MMU
  77
  78   mcr     p15,0,R0,c8,c7,0      @Invalidate TLB
  79   mcr     p15,0,R0,c7,c5,6      @Invalidate Branch predictor array
  80   dsb
  81   isb
  82   bx      LR
  83
  84 ASM_FUNC(ArmDisableCachesAndMmu)
  85   mrc   p15, 0, r0, c1, c0, 0           @ Get control register
  86   bic   r0, r0, #CTRL_M_BIT             @ Disable MMU
  87   bic   r0, r0, #CTRL_C_BIT             @ Disable D Cache
  88   bic   r0, r0, #CTRL_I_BIT             @ Disable I Cache
  89   mcr   p15, 0, r0, c1, c0, 0           @ Write control register
  90   dsb
  91   isb
  92   bx      LR
  93
  94 ASM_FUNC(ArmMmuEnabled)
  95   mrc     p15,0,R0,c1,c0,0
  96   and     R0,R0,#1
  97   bx      LR
  98
  99 ASM_FUNC(ArmEnableDataCache)
 100   ldr     R1,=DC_ON
 101   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 102   orr     R0,R0,R1              @Set C bit
 103   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 104   dsb
 105   isb
 106   bx      LR
 107
 108 ASM_FUNC(ArmDisableDataCache)
 109   ldr     R1,=DC_ON
 110   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 111   bic     R0,R0,R1              @Clear C bit
 112   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 113   dsb
 114   isb
 115   bx      LR
 116
 117 ASM_FUNC(ArmEnableInstructionCache)
 118   ldr     R1,=IC_ON
 119   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 120   orr     R0,R0,R1              @Set I bit
 121   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 122   dsb
 123   isb
 124   bx      LR
 125
 126 ASM_FUNC(ArmDisableInstructionCache)
 127   ldr     R1,=IC_ON
 128   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 129   bic     R0,R0,R1              @Clear I bit.
 130   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 131   dsb
 132   isb
 133   bx      LR
 134
 135 ASM_FUNC(ArmEnableSWPInstruction)
 136   mrc     p15, 0, r0, c1, c0, 0
 137   orr     r0, r0, #0x00000400
 138   mcr     p15, 0, r0, c1, c0, 0
 139   isb
 140   bx      LR
 141
 142 ASM_FUNC(ArmEnableBranchPrediction)
 143   mrc     p15, 0, r0, c1, c0, 0
 144   orr     r0, r0, #0x00000800
 145   mcr     p15, 0, r0, c1, c0, 0
 146   dsb
 147   isb
 148   bx      LR
 149
 150 ASM_FUNC(ArmDisableBranchPrediction)
 151   mrc     p15, 0, r0, c1, c0, 0
 152   bic     r0, r0, #0x00000800
 153   mcr     p15, 0, r0, c1, c0, 0
 154   dsb
 155   isb
 156   bx      LR
 157
 158 ASM_FUNC(ArmSetLowVectors)
 159   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 160   bic     r0, r0, #0x00002000   @ clear V bit
 161   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 162   isb
 163   bx      LR
 164
 165 ASM_FUNC(ArmSetHighVectors)
 166   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 167   orr     r0, r0, #0x00002000   @ Set V bit
 168   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 169   isb
 170   bx      LR
 171
 172 ASM_FUNC(ArmV7AllDataCachesOperation)
 173   stmfd SP!,{r4-r12, LR}
 174   mov   R1, R0                @ Save Function call in R1
 175   mrc   p15, 1, R6, c0, c0, 1 @ Read CLIDR
 176   ands  R3, R6, #0x7000000    @ Mask out all but Level of Coherency (LoC)
 177   mov   R3, R3, LSR #23       @ Cache level value (naturally aligned)
 178   beq   L_Finished
 179   mov   R10, #0
 180
 181 Loop1:
 182   add   R2, R10, R10, LSR #1  @ Work out 3xcachelevel
 183   mov   R12, R6, LSR R2       @ bottom 3 bits are the Cache type for this level
 184   and   R12, R12, #7          @ get those 3 bits alone
 185   cmp   R12, #2
 186   blt   L_Skip                  @ no cache or only instruction cache at this level
 187   mcr   p15, 2, R10, c0, c0, 0  @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
 188   isb                           @ isb to sync the change to the CacheSizeID reg
 189   mrc   p15, 1, R12, c0, c0, 0  @ reads current Cache Size ID register (CCSIDR)
 190   and   R2, R12, #0x7           @ extract the line length field
 191   add   R2, R2, #4              @ add 4 for the line length offset (log2 16 bytes)
 192 @  ldr   R4, =0x3FF
 193   mov   R4, #0x400
 194   sub   R4, R4, #1
 195   ands  R4, R4, R12, LSR #3     @ R4 is the max number on the way size (right aligned)
 196   clz   R5, R4                  @ R5 is the bit position of the way size increment
 197 @  ldr   R7, =0x00007FFF
 198   mov   R7, #0x00008000
 199   sub   R7, R7, #1
 200   ands  R7, R7, R12, LSR #13    @ R7 is the max number of the index size (right aligned)
 201
 202 Loop2:
 203   mov   R9, R4                  @ R9 working copy of the max way size (right aligned)
 204
 205 Loop3:
 206   orr   R0, R10, R9, LSL R5     @ factor in the way number and cache number into R11
 207   orr   R0, R0, R7, LSL R2      @ factor in the index number
 208
 209   blx   R1
 210
 211   subs  R9, R9, #1              @ decrement the way number
 212   bge   Loop3
 213   subs  R7, R7, #1              @ decrement the index
 214   bge   Loop2
 215 L_Skip:
 216   add   R10, R10, #2            @ increment the cache number
 217   cmp   R3, R10
 218   bgt   Loop1
 219
 220 L_Finished:
 221   dsb
 222   ldmfd SP!, {r4-r12, lr}
 223   bx    LR
 224
 225 ASM_FUNC(ArmDataMemoryBarrier)
 226   dmb
 227   bx      LR
 228
 229 ASM_FUNC(ArmDataSynchronizationBarrier)
 230   dsb
 231   bx      LR
 232
 233 ASM_FUNC(ArmInstructionSynchronizationBarrier)
 234   isb
 235   bx      LR
 236
 237 ASM_FUNC(ArmReadVBar)
 238   # Set the Address of the Vector Table in the VBAR register
 239   mrc     p15, 0, r0, c12, c0, 0
 240   bx      lr
 241
 242 ASM_FUNC(ArmWriteVBar)
 243   # Set the Address of the Vector Table in the VBAR register
 244   mcr     p15, 0, r0, c12, c0, 0
 245   # Ensure the SCTLR.V bit is clear
 246   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 247   bic     r0, r0, #0x00002000   @ clear V bit
 248   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 249   isb
 250   bx      lr
 251
 252 ASM_FUNC(ArmEnableVFP)
 253   # Read CPACR (Coprocessor Access Control Register)
 254   mrc     p15, 0, r0, c1, c0, 2
 255   # Enable VPF access (Full Access to CP10, CP11) (V* instructions)
 256   orr     r0, r0, #0x00f00000
 257   # Write back CPACR (Coprocessor Access Control Register)
 258   mcr     p15, 0, r0, c1, c0, 2
 259   isb
 260   # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
 261   mov     r0, #0x40000000
 262 #ifndef __clang__
 263   mcr     p10,#0x7,r0,c8,c0,#0
 264 #else
 265   vmsr    fpexc, r0
 266 #endif
 267   bx      lr
 268
 269 ASM_FUNC(ArmCallWFI)
 270   wfi
 271   bx      lr
 272
 273 #Note: Return 0 in Uniprocessor implementation
 274 ASM_FUNC(ArmReadCbar)
 275   mrc     p15, 4, r0, c15, c0, 0  @ Read Configuration Base Address Register
 276   bx      lr
 277
 278 ASM_FUNC(ArmReadMpidr)
 279   mrc     p15, 0, r0, c0, c0, 5       @ read MPIDR
 280   bx      lr
 281
 282 ASM_FUNC(ArmReadTpidrurw)
 283   mrc     p15, 0, r0, c13, c0, 2    @ read TPIDRURW
 284   bx      lr
 285
 286 ASM_FUNC(ArmWriteTpidrurw)
 287   mcr     p15, 0, r0, c13, c0, 2    @ write TPIDRURW
 288   bx      lr
 289
 290 ASM_FUNC(ArmIsArchTimerImplemented)
 291   mrc    p15, 0, r0, c0, c1, 1     @ Read ID_PFR1
 292   and    r0, r0, #0x000F0000
 293   bx     lr
 294
 295 ASM_FUNC(ArmReadIdPfr1)
 296   mrc    p15, 0, r0, c0, c1, 1     @ Read ID_PFR1 Register
 297   bx     lr
 298
 299 ASM_FUNCTION_REMOVE_IF_UNREFERENCED