ArmPkg/Library/ArmLib/Arm11/Arm11Support.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 #
   5 # This program and the accompanying materials
   6 # are licensed and made available under the terms and conditions of the BSD License
   7 # which accompanies this distribution.  The full text of the license may be found at
   8 # http://opensource.org/licenses/bsd-license.php
   9 #
  10 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 #
  13 #------------------------------------------------------------------------------
  14
  15 #include <AsmMacroIoLib.h>
  16
  17 .text
  18 .align 2
  19 GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)
  20 GCC_ASM_EXPORT(ArmCleanDataCache)
  21 GCC_ASM_EXPORT(ArmInvalidateDataCache)
  22 GCC_ASM_EXPORT(ArmInvalidateInstructionCache)
  23 GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)
  24 GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)
  25 GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)
  26 GCC_ASM_EXPORT(ArmEnableMmu)
  27 GCC_ASM_EXPORT(ArmDisableMmu)
  28 GCC_ASM_EXPORT(ArmMmuEnabled)
  29 GCC_ASM_EXPORT(ArmEnableDataCache)
  30 GCC_ASM_EXPORT(ArmDisableDataCache)
  31 GCC_ASM_EXPORT(ArmEnableInstructionCache)
  32 GCC_ASM_EXPORT(ArmDisableInstructionCache)
  33 GCC_ASM_EXPORT(ArmEnableBranchPrediction)
  34 GCC_ASM_EXPORT(ArmDisableBranchPrediction)
  35 GCC_ASM_EXPORT(ArmDataMemoryBarrier)
  36 GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)
  37 GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)
  38
  39
  40 .set DC_ON, (0x1<<2)
  41 .set IC_ON, (0x1<<12)
  42 .set XP_ON, (0x1<<23)
  43
  44 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
  45   mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line
  46   bx      lr
  47
  48
  49 ASM_PFX(ArmCleanDataCacheEntryByMVA):
  50   mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line
  51   bx      lr
  52
  53
  54 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
  55   mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line
  56   bx      lr
  57
  58
  59 ASM_PFX(ArmCleanDataCache):
  60   mcr     p15, 0, r0, c7, c10, 0  @ clean entire data cache
  61   bx      lr
  62
  63
  64 ASM_PFX(ArmCleanInvalidateDataCache):
  65   mcr     p15, 0, r0, c7, c14, 0  @ clean and invalidate entire data cache
  66   bx      lr
  67
  68
  69 ASM_PFX(ArmInvalidateDataCache):
  70   mcr     p15, 0, r0, c7, c6, 0  @ invalidate entire data cache
  71   bx      lr
  72
  73
  74 ASM_PFX(ArmInvalidateInstructionCache):
  75   mcr     p15, 0, r0, c7, c5, 0  @invalidate entire instruction cache
  76   mov     R0,#0
  77   mcr     p15,0,R0,c7,c5,4       @Flush Prefetch buffer
  78   bx      lr
  79
  80 ASM_PFX(ArmEnableMmu):
  81   mrc     p15,0,R0,c1,c0,0
  82   orr     R0,R0,#1
  83   mcr     p15,0,R0,c1,c0,0
  84   bx      LR
  85
  86 ASM_PFX(ArmMmuEnabled):
  87   mrc     p15,0,R0,c1,c0,0
  88   and     R0,R0,#1
  89   bx      LR
  90
  91 ASM_PFX(ArmDisableMmu):
  92   mrc     p15,0,R0,c1,c0,0
  93   bic     R0,R0,#1
  94   mcr     p15,0,R0,c1,c0,0
  95   mov     R0,#0
  96   mcr     p15,0,R0,c7,c10,4     @Data synchronization barrier
  97   mov     R0,#0
  98   mcr     p15,0,R0,c7,c5,4      @Flush Prefetch buffer
  99   bx      LR
 100
 101 ASM_PFX(ArmEnableDataCache):
 102   LoadConstantToReg(DC_ON, R1)  @ldr     R1,=DC_ON
 103   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 104   orr     R0,R0,R1              @Set C bit
 105   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 106   bx      LR
 107
 108 ASM_PFX(ArmDisableDataCache):
 109   LoadConstantToReg(DC_ON, R1)  @ldr     R1,=DC_ON
 110   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 111   bic     R0,R0,R1              @Clear C bit
 112   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 113   bx      LR
 114
 115 ASM_PFX(ArmEnableInstructionCache):
 116   ldr     R1,=IC_ON
 117   mrc     p15,0,R0,c1,c0,0     @Read control register configuration data
 118   orr     R0,R0,R1             @Set I bit
 119   mcr     p15,0,r0,c1,c0,0     @Write control register configuration data
 120   bx      LR
 121
 122 ASM_PFX(ArmDisableInstructionCache):
 123   ldr     R1,=IC_ON
 124   mrc     p15,0,R0,c1,c0,0     @Read control register configuration data
 125   bic     R0,R0,R1             @Clear I bit.
 126   mcr     p15,0,r0,c1,c0,0     @Write control register configuration data
 127   bx      LR
 128
 129 ASM_PFX(ArmEnableBranchPrediction):
 130   mrc     p15, 0, r0, c1, c0, 0
 131   orr     r0, r0, #0x00000800
 132   mcr     p15, 0, r0, c1, c0, 0
 133   bx      LR
 134
 135 ASM_PFX(ArmDisableBranchPrediction):
 136   mrc     p15, 0, r0, c1, c0, 0
 137   bic     r0, r0, #0x00000800
 138   mcr     p15, 0, r0, c1, c0, 0
 139   bx      LR
 140
 141 ASM_PFX(ArmDataMemoryBarrier):
 142   mov R0, #0
 143   mcr P15, #0, R0, C7, C10, #5
 144   bx      LR
 145
 146 ASM_PFX(ArmDataSyncronizationBarrier):
 147   mov R0, #0
 148   mcr P15, #0, R0, C7, C10, #4
 149   bx      LR
 150
 151 ASM_PFX(ArmInstructionSynchronizationBarrier):
 152   mov R0, #0
 153   mcr P15, #0, R0, C7, C5, #4
 154   bx      LR
 155
 156
 157 ASM_FUNCTION_REMOVE_IF_UNREFERENCED