ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008-2009 Apple Inc. All rights reserved.
   4 //
   5 // All rights reserved. This program and the accompanying materials
   6 // are licensed and made available under the terms and conditions of the BSD License
   7 // which accompanies this distribution.  The full text of the license may be found at
   8 // http://opensource.org/licenses/bsd-license.php
   9 //
  10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 //
  13 //------------------------------------------------------------------------------
  14
  15     EXPORT  ArmCleanInvalidateDataCache
  16     EXPORT  ArmCleanDataCache
  17     EXPORT  ArmInvalidateDataCache
  18     EXPORT  ArmInvalidateInstructionCache
  19     EXPORT  ArmInvalidateDataCacheEntryByMVA
  20     EXPORT  ArmCleanDataCacheEntryByMVA
  21     EXPORT  ArmCleanInvalidateDataCacheEntryByMVA
  22     EXPORT  ArmEnableMmu
  23     EXPORT  ArmDisableMmu
  24     EXPORT  ArmEnableDataCache
  25     EXPORT  ArmDisableDataCache
  26     EXPORT  ArmEnableInstructionCache
  27     EXPORT  ArmDisableInstructionCache
  28     EXPORT  ArmEnableBranchPrediction
  29     EXPORT  ArmDisableBranchPrediction
  30
  31
  32 DC_ON       EQU     ( 0x1:SHL:2 )
  33 IC_ON       EQU     ( 0x1:SHL:12 )
  34
  35     AREA    ArmCacheLib, CODE, READONLY
  36     PRESERVE8
  37
  38
  39 ArmInvalidateDataCacheEntryByMVA
  40   MCR     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line
  41   BX      lr
  42
  43
  44 ArmCleanDataCacheEntryByMVA
  45   MCR     p15, 0, r0, c7, c10, 1  ; clean single data cache line
  46   BX      lr
  47
  48
  49 ArmCleanInvalidateDataCacheEntryByMVA
  50   MCR     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line
  51   BX      lr
  52
  53 ArmEnableInstructionCache
  54   LDR     R1,=IC_ON
  55   MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data
  56   ORR     R0,R0,R1             ;Set I bit
  57   MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data
  58   BX      LR
  59
  60 ArmDisableInstructionCache
  61   LDR     R1,=IC_ON
  62   MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data
  63   BIC     R0,R0,R1             ;Clear I bit.
  64   MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data
  65   BX      LR
  66
  67 ArmInvalidateInstructionCache
  68   MOV     R0,#0
  69   MCR     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache
  70   MOV     R0,#0
  71   MCR     p15,0,R0,c7,c10,4     ;Drain write buffer
  72   BX      LR
  73
  74 ArmEnableMmu
  75   mrc     p15,0,R0,c1,c0,0
  76   orr     R0,R0,#1
  77   mcr     p15,0,R0,c1,c0,0
  78   bx      LR
  79
  80 ArmDisableMmu
  81   mrc     p15,0,R0,c1,c0,0
  82   bic     R0,R0,#1
  83   mcr     p15,0,R0,c1,c0,0
  84   mov     R0,#0
  85   mcr     p15,0,R0,c7,c10,4     ;Drain write buffer
  86   bx      LR
  87
  88 ArmEnableDataCache
  89   LDR     R1,=DC_ON
  90   MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
  91   ORR     R0,R0,R1              ;Set C bit
  92   MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
  93   BX      LR
  94
  95 ArmDisableDataCache
  96   LDR     R1,=DC_ON
  97   MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
  98   BIC     R0,R0,R1              ;Clear C bit
  99   MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
 100   BX      LR
 101
 102 ArmCleanDataCache
 103   MRC     p15,0,r15,c7,c10,3
 104   BNE     ArmCleanDataCache
 105   MOV     R0,#0
 106   MCR     p15,0,R0,c7,c10,4         ;Drain write buffer
 107   BX      LR
 108
 109 ArmInvalidateDataCache
 110   MOV     R0,#0
 111   MCR     p15,0,R0,c7,c6,0      ;Invalidate entire data cache
 112   MOV     R0,#0
 113   MCR     p15,0,R0,c7,c10,4     ;Drain write buffer
 114   BX      LR
 115
 116 ArmCleanInvalidateDataCache
 117   MRC     p15,0,r15,c7,c14,3
 118   BNE     ArmCleanInvalidateDataCache
 119   MOV     R0,#0
 120   MCR     p15,0,R0,c7,c10,4         ;Drain write buffer
 121   BX      LR
 122
 123 ArmEnableBranchPrediction
 124   bx      LR                    ;Branch prediction is not supported.
 125
 126 ArmDisableBranchPrediction
 127   bx      LR                    ;Branch prediction is not supported.
 128
 129     END