ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexASupport.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008-2009 Apple Inc. All rights reserved.
   4 #
   5 # All rights reserved. This program and the accompanying materials
   6 # are licensed and made available under the terms and conditions of the BSD License
   7 # which accompanies this distribution.  The full text of the license may be found at
   8 # http://opensource.org/licenses/bsd-license.php
   9 #
  10 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 #
  13 #------------------------------------------------------------------------------
  14
  15 .text
  16 .align 2
  17 .globl ASM_PFX(ArmInvalidateInstructionCache)
  18 .globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
  19 .globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
  20 .globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA)
  21 .globl ASM_PFX(ArmInvalidateDataCacheEntryBySetWay)
  22 .globl ASM_PFX(ArmCleanDataCacheEntryBySetWay)
  23 .globl ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay)
  24 .globl ASM_PFX(ArmDrainWriteBuffer)
  25 .globl ASM_PFX(ArmEnableMmu)
  26 .globl ASM_PFX(ArmDisableMmu)
  27 .globl ASM_PFX(ArmEnableDataCache)
  28 .globl ASM_PFX(ArmDisableDataCache)
  29 .globl ASM_PFX(ArmEnableInstructionCache)
  30 .globl ASM_PFX(ArmDisableInstructionCache)
  31 .globl ASM_PFX(ArmEnableExtendPTConfig)
  32 .globl ASM_PFX(ArmDisableExtendPTConfig)
  33 .globl ASM_PFX(ArmEnableBranchPrediction)
  34 .globl ASM_PFX(ArmDisableBranchPrediction)
  35
  36 .set DC_ON, (0x1<<2)
  37 .set IC_ON, (0x1<<12)
  38 .set XP_ON, (0x1<<23)
  39
  40 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
  41   mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line
  42   bx      lr
  43
  44
  45 ASM_PFX(ArmCleanDataCacheEntryByMVA):
  46   mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line
  47   bx      lr
  48
  49
  50 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
  51   mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line
  52   bx      lr
  53
  54
  55 ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
  56   mcr     p15, 0, r0, c7, c6, 2        @ Invalidate this line
  57   bx      lr
  58
  59
  60 ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
  61   mcr     p15, 0, r0, c7, c14, 2       @ Clean and Invalidate this line
  62   bx      lr
  63
  64
  65 ASM_PFX(ArmCleanDataCacheEntryBySetWay):
  66   mcr     p15, 0, r0, c7, c10, 2       @ Clean this line
  67   bx      lr
  68
  69
  70 ASM_PFX(ArmDrainWriteBuffer):
  71   mcr     p15, 0, r0, c7, c10, 4       @ Drain write buffer for sync
  72   bx      lr
  73
  74
  75 ASM_PFX(ArmInvalidateInstructionCache):
  76   mov     R0,#0
  77   mcr     p15,0,R0,c7,c5,0      @Invalidate entire instruction cache
  78   mov     R0,#0
  79   mcr     p15,0,R0,c7,c5,4      @Instruction synchronization barrier
  80   bx      LR
  81
  82 ASM_PFX(ArmEnableMmu):
  83   mrc     p15,0,R0,c1,c0,0
  84   orr     R0,R0,#1
  85   mcr     p15,0,R0,c1,c0,0
  86   bx      LR
  87
  88 ASM_PFX(ArmDisableMmu):
  89   mov     R0,#0
  90   mcr     p15,0,R0,c13,c0,0     @FCSE PID register must be cleared before disabling MMU
  91   mrc     p15,0,R0,c1,c0,0
  92   bic     R0,R0,#1
  93   mcr     p15,0,R0,c1,c0,0      @Disable MMU
  94   mov     R0,#0
  95   mcr     p15,0,R0,c7,c10,4     @Data synchronization barrier
  96   mov     R0,#0
  97   mcr     p15,0,R0,c7,c5,4      @Instruction synchronization barrier
  98   bx      LR
  99
 100 ASM_PFX(ArmEnableDataCache):
 101   ldr     R1,=DC_ON
 102   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 103   orr     R0,R0,R1              @Set C bit
 104   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 105   bx      LR
 106
 107 ASM_PFX(ArmDisableDataCache):
 108   ldr     R1,=DC_ON
 109   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 110   bic     R0,R0,R1              @Clear C bit
 111   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 112   bx      LR
 113
 114 ASM_PFX(ArmEnableInstructionCache):
 115   ldr     R1,=IC_ON
 116   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 117   orr     R0,R0,R1              @Set I bit
 118   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 119   bx      LR
 120
 121 ASM_PFX(ArmDisableInstructionCache):
 122   ldr     R1,=IC_ON
 123   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 124   bic     R0,R0,R1              @Clear I bit.
 125   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 126   bx      LR
 127
 128 ASM_PFX(ArmEnableBranchPrediction):
 129   mrc     p15, 0, r0, c1, c0, 0
 130   orr     r0, r0, #0x00000800
 131   mcr     p15, 0, r0, c1, c0, 0
 132   bx      LR
 133
 134 ASM_PFX(ArmDisableBranchPrediction):
 135   mrc     p15, 0, r0, c1, c0, 0
 136   bic     r0, r0, #0x00000800
 137   mcr     p15, 0, r0, c1, c0, 0
 138   bx      LR
 139
 140 ASM_FUNCTION_REMOVE_IF_UNREFERENCED