1 //------------------------------------------------------------------------------
3 // Copyright (c) 2008-2009 Apple Inc. All rights reserved.
5 // All rights reserved. This program and the accompanying materials
6 // are licensed and made available under the terms and conditions of the BSD License
7 // which accompanies this distribution. The full text of the license may be found at
8 // http://opensource.org/licenses/bsd-license.php
10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 //------------------------------------------------------------------------------
15 EXPORT ArmInvalidateInstructionCache
16 EXPORT ArmInvalidateDataCacheEntryByMVA
17 EXPORT ArmCleanDataCacheEntryByMVA
18 EXPORT ArmCleanInvalidateDataCacheEntryByMVA
19 EXPORT ArmInvalidateDataCacheEntryBySetWay
20 EXPORT ArmCleanDataCacheEntryBySetWay
21 EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
22 EXPORT ArmDrainWriteBuffer
25 EXPORT ArmEnableDataCache
26 EXPORT ArmDisableDataCache
27 EXPORT ArmEnableInstructionCache
28 EXPORT ArmDisableInstructionCache
29 EXPORT ArmEnableBranchPrediction
30 EXPORT ArmDisableBranchPrediction
32 DC_ON EQU ( 0x1:SHL:2 )
33 IC_ON EQU ( 0x1:SHL:12 )
34 XP_ON EQU ( 0x1:SHL:23 )
37 AREA ArmCacheLib, CODE, READONLY
41 ArmInvalidateDataCacheEntryByMVA
42 MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
46 ArmCleanDataCacheEntryByMVA
47 MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
51 ArmCleanInvalidateDataCacheEntryByMVA
52 MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
56 ArmInvalidateDataCacheEntryBySetWay
57 mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
61 ArmCleanInvalidateDataCacheEntryBySetWay
62 mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
66 ArmCleanDataCacheEntryBySetWay
67 mcr p15, 0, r0, c7, c10, 2 ; Clean this line
72 mcr p15, 0, r0, c7, c10, 4 ; Drain write buffer for sync
76 ArmInvalidateInstructionCache
78 MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
80 MCR p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
91 mcr p15,0,R0,c13,c0,0 ;FCSE PID register must be cleared before disabling MMU
94 mcr p15,0,R0,c1,c0,0 ;Disable MMU
96 mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier
98 mcr p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
103 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
104 ORR R0,R0,R1 ;Set C bit
105 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
110 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
111 BIC R0,R0,R1 ;Clear C bit
112 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
115 ArmEnableInstructionCache
117 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
118 ORR R0,R0,R1 ;Set I bit
119 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
122 ArmDisableInstructionCache
124 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
125 BIC R0,R0,R1 ;Clear I bit.
126 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
129 ArmEnableBranchPrediction
130 mrc p15, 0, r0, c1, c0, 0
131 orr r0, r0, #0x00000800
132 mcr p15, 0, r0, c1, c0, 0
135 ArmDisableBranchPrediction
136 mrc p15, 0, r0, c1, c0, 0
137 bic r0, r0, #0x00000800
138 mcr p15, 0, r0, c1, c0, 0