1 //------------------------------------------------------------------------------
3 // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
5 // This program and the accompanying materials
6 // are licensed and made available under the terms and conditions of the BSD License
7 // which accompanies this distribution. The full text of the license may be found at
8 // http://opensource.org/licenses/bsd-license.php
10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 //------------------------------------------------------------------------------
19 EXPORT ArmEnableAsynchronousAbort
20 EXPORT ArmDisableAsynchronousAbort
23 EXPORT ArmGetInterruptState
26 EXPORT ArmEnableInterrupts
27 EXPORT ArmDisableInterrupts
29 EXPORT ArmInvalidateTlb
31 EXPORT ArmGetTTBR0BaseAddress
32 EXPORT ArmSetDomainAccessControl
33 EXPORT ArmUpdateTranslationTableEntry
39 AREA ArmLibSupport, CODE, READONLY
42 //------------------------------------------------------------------------------
54 // Get Multiprocessing extension (bit31) & U bit (bit30)
55 and R0, R0, #0xC0000000
56 // if bit30 == 0 then the processor is part of a multiprocessor system)
57 and R0, R0, #0x80000000
60 ArmEnableAsynchronousAbort
65 ArmDisableAsynchronousAbort
102 tst R0,#0x80\s\s ;Check if IRQ is enabled.
109 \s\stst R0,#0x40\s\s ;Check if FIQ is enabled.
117 mcr p15,0,R9,c7,c5,6 ; BPIALL Invalidate Branch predictor array. R9 == NoOp
127 ArmGetTTBR0BaseAddress
129 ldr\s\s r1, = 0xFFFFC000
135 ArmSetDomainAccessControl
142 //ArmUpdateTranslationTableEntry (
143 // IN VOID *TranslationTableEntry // R0
144 // IN VOID *MVA // R1
146 ArmUpdateTranslationTableEntry
147 mcr p15,0,R0,c7,c14,1 ; DCCIMVAC Clean data cache by MVA
149 mcr p15,0,R1,c8,c7,1 ; TLBIMVA TLB Invalidate MVA
150 mcr p15,0,R9,c7,c5,6 ; BPIALL Invalidate Branch predictor array. R9 == NoOp
155 CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to insert
156 stmfd sp!, {r4-r12, lr} ; save all the banked registers
157 mov r3, sp ; copy the stack pointer into a non-banked register
158 mrs r2, cpsr ; read the cpsr
159 bic r2, r2, r0 ; clear mask in the cpsr
160 and r1, r1, r0 ; clear bits outside the mask in the input
161 orr r2, r2, r1 ; set field
162 msr cpsr_cxsf, r2 ; write back cpsr (may have caused a mode switch)
164 mov sp, r3 ; restore stack pointer
165 ldmfd sp!, {r4-r12, lr} ; restore registers
166 bx lr ; return (hopefully thumb-safe!)
178 mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)
180 mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
189 mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register