ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011, ARM Limited. All rights reserved.
   5 #
   6 # This program and the accompanying materials
   7 # are licensed and made available under the terms and conditions of the BSD License
   8 # which accompanies this distribution.  The full text of the license may be found at
   9 # http://opensource.org/licenses/bsd-license.php
  10 #
  11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 #
  14 #------------------------------------------------------------------------------
  15
  16 #include <AsmMacroIoLib.h>
  17
  18 .text
  19 .align 2
  20
  21 GCC_ASM_EXPORT(ArmIsMpCore)
  22 GCC_ASM_EXPORT(ArmEnableAsynchronousAbort)
  23 GCC_ASM_EXPORT(ArmDisableAsynchronousAbort)
  24 GCC_ASM_EXPORT(ArmEnableIrq)
  25 GCC_ASM_EXPORT(ArmDisableIrq)
  26 GCC_ASM_EXPORT(ArmEnableFiq)
  27 GCC_ASM_EXPORT(ArmDisableFiq)
  28 GCC_ASM_EXPORT(ArmEnableInterrupts)
  29 GCC_ASM_EXPORT(ArmDisableInterrupts)
  30 GCC_ASM_EXPORT(ReadCCSIDR)
  31 GCC_ASM_EXPORT(ReadCLIDR)
  32
  33 #------------------------------------------------------------------------------
  34
  35 ASM_PFX(ArmIsMpCore):
  36   mrc     p15,0,R0,c0,c0,5
  37   // Get Multiprocessing extension (bit31) & U bit (bit30)
  38   and     R0, R0, #0xC0000000
  39   // if bit30 == 0 then the processor is part of a multiprocessor system)
  40   and     R0, R0, #0x80000000
  41   bx      LR
  42
  43 ASM_PFX(ArmEnableAsynchronousAbort):
  44   cpsie   a
  45   isb
  46   bx      LR
  47
  48 ASM_PFX(ArmDisableAsynchronousAbort):
  49   cpsid   a
  50   isb
  51   bx      LR
  52
  53 ASM_PFX(ArmEnableIrq):
  54   cpsie   i
  55   isb
  56   bx      LR
  57
  58 ASM_PFX(ArmDisableIrq):
  59   cpsid   i
  60   isb
  61   bx      LR
  62
  63 ASM_PFX(ArmEnableFiq):
  64   cpsie   f
  65   isb
  66   bx      LR
  67
  68 ASM_PFX(ArmDisableFiq):
  69   cpsid   f
  70   isb
  71   bx      LR
  72
  73 ASM_PFX(ArmEnableInterrupts):
  74   cpsie   if
  75   isb
  76   bx      LR
  77
  78 ASM_PFX(ArmDisableInterrupts):
  79   cpsid   if
  80   isb
  81   bx      LR
  82
  83 // UINT32
  84 // ReadCCSIDR (
  85 //   IN UINT32 CSSELR
  86 //   )
  87 ASM_PFX(ReadCCSIDR):
  88   mcr p15,2,r0,c0,c0,0   @ Write Cache Size Selection Register (CSSELR)
  89   isb
  90   mrc p15,1,r0,c0,c0,0   @ Read current CP15 Cache Size ID Register (CCSIDR)
  91   bx  lr
  92
  93 // UINT32
  94 // ReadCLIDR (
  95 //   IN UINT32 CSSELR
  96 //   )
  97 ASM_PFX(ReadCLIDR):
  98   mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register
  99   bx  lr
 100
 101 ASM_FUNCTION_REMOVE_IF_UNREFERENCED