ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011-2013, ARM Limited. All rights reserved.
   5 #
   6 # This program and the accompanying materials
   7 # are licensed and made available under the terms and conditions of the BSD License
   8 # which accompanies this distribution.  The full text of the license may be found at
   9 # http://opensource.org/licenses/bsd-license.php
  10 #
  11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 #
  14 #------------------------------------------------------------------------------
  15
  16 #include <AsmMacroIoLib.h>
  17
  18 .text
  19 .align 2
  20
  21 GCC_ASM_EXPORT(ArmIsMpCore)
  22 GCC_ASM_EXPORT(ArmEnableAsynchronousAbort)
  23 GCC_ASM_EXPORT(ArmDisableAsynchronousAbort)
  24 GCC_ASM_EXPORT(ArmEnableIrq)
  25 GCC_ASM_EXPORT(ArmDisableIrq)
  26 GCC_ASM_EXPORT(ArmEnableFiq)
  27 GCC_ASM_EXPORT(ArmDisableFiq)
  28 GCC_ASM_EXPORT(ArmEnableInterrupts)
  29 GCC_ASM_EXPORT(ArmDisableInterrupts)
  30 GCC_ASM_EXPORT(ReadCCSIDR)
  31 GCC_ASM_EXPORT(ReadCLIDR)
  32 GCC_ASM_EXPORT(ArmReadNsacr)
  33 GCC_ASM_EXPORT(ArmWriteNsacr)
  34
  35 #------------------------------------------------------------------------------
  36
  37 ASM_PFX(ArmIsMpCore):
  38   mrc     p15,0,R0,c0,c0,5
  39   // Get Multiprocessing extension (bit31) & U bit (bit30)
  40   and     R0, R0, #0xC0000000
  41   // if (bit31 == 1) && (bit30 == 0) then the processor is part of a multiprocessor system
  42   cmp     R0, #0x80000000
  43   moveq   R0, #1
  44   movne   R0, #0
  45   bx      LR
  46
  47 ASM_PFX(ArmEnableAsynchronousAbort):
  48   cpsie   a
  49   isb
  50   bx      LR
  51
  52 ASM_PFX(ArmDisableAsynchronousAbort):
  53   cpsid   a
  54   isb
  55   bx      LR
  56
  57 ASM_PFX(ArmEnableIrq):
  58   cpsie   i
  59   isb
  60   bx      LR
  61
  62 ASM_PFX(ArmDisableIrq):
  63   cpsid   i
  64   isb
  65   bx      LR
  66
  67 ASM_PFX(ArmEnableFiq):
  68   cpsie   f
  69   isb
  70   bx      LR
  71
  72 ASM_PFX(ArmDisableFiq):
  73   cpsid   f
  74   isb
  75   bx      LR
  76
  77 ASM_PFX(ArmEnableInterrupts):
  78   cpsie   if
  79   isb
  80   bx      LR
  81
  82 ASM_PFX(ArmDisableInterrupts):
  83   cpsid   if
  84   isb
  85   bx      LR
  86
  87 // UINT32
  88 // ReadCCSIDR (
  89 //   IN UINT32 CSSELR
  90 //   )
  91 ASM_PFX(ReadCCSIDR):
  92   mcr p15,2,r0,c0,c0,0   @ Write Cache Size Selection Register (CSSELR)
  93   isb
  94   mrc p15,1,r0,c0,c0,0   @ Read current CP15 Cache Size ID Register (CCSIDR)
  95   bx  lr
  96
  97 // UINT32
  98 // ReadCLIDR (
  99 //   IN UINT32 CSSELR
 100 //   )
 101 ASM_PFX(ReadCLIDR):
 102   mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register
 103   bx  lr
 104
 105 ASM_PFX(ArmReadNsacr):
 106   mrc     p15, 0, r0, c1, c1, 2
 107   bx      lr
 108
 109 ASM_PFX(ArmWriteNsacr):
 110   mcr     p15, 0, r0, c1, c1, 2
 111   bx      lr
 112
 113 ASM_FUNCTION_REMOVE_IF_UNREFERENCED