ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
   4 // Copyright (c) 2011-2013, ARM Limited. All rights reserved.
   5 //
   6 // This program and the accompanying materials
   7 // are licensed and made available under the terms and conditions of the BSD License
   8 // which accompanies this distribution.  The full text of the license may be found at
   9 // http://opensource.org/licenses/bsd-license.php
  10 //
  11 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 //
  14 //------------------------------------------------------------------------------
  15
  16
  17     EXPORT  ArmIsMpCore
  18     EXPORT  ArmHasMpExtensions
  19     EXPORT  ArmEnableAsynchronousAbort
  20     EXPORT  ArmDisableAsynchronousAbort
  21     EXPORT  ArmEnableIrq
  22     EXPORT  ArmDisableIrq
  23     EXPORT  ArmEnableFiq
  24     EXPORT  ArmDisableFiq
  25     EXPORT  ArmEnableInterrupts
  26     EXPORT  ArmDisableInterrupts
  27     EXPORT  ReadCCSIDR
  28     EXPORT  ReadCLIDR
  29     EXPORT  ArmReadNsacr
  30     EXPORT  ArmWriteNsacr
  31
  32     AREA ArmLibSupportV7, CODE, READONLY
  33
  34
  35 //------------------------------------------------------------------------------
  36
  37 ArmIsMpCore
  38   mrc     p15,0,R0,c0,c0,5
  39   // Get Multiprocessing extension (bit31) & U bit (bit30)
  40   and     R0, R0, #0xC0000000
  41   // if (bit31 == 1) && (bit30 == 0) then the processor is part of a multiprocessor system
  42   cmp     R0, #0x80000000
  43   moveq   R0, #1
  44   movne   R0, #0
  45   bx      LR
  46
  47 ArmHasMpExtensions
  48   mrc     p15,0,R0,c0,c0,5
  49   // Get Multiprocessing extension (bit31)
  50   lsr     R0, R0, #31
  51   bx      LR
  52
  53 ArmEnableAsynchronousAbort
  54   cpsie   a
  55   isb
  56   bx      LR
  57
  58 ArmDisableAsynchronousAbort
  59   cpsid   a
  60   isb
  61   bx      LR
  62
  63 ArmEnableIrq
  64   cpsie   i
  65   isb
  66   bx      LR
  67
  68 ArmDisableIrq
  69   cpsid   i
  70   isb
  71   bx      LR
  72
  73 ArmEnableFiq
  74   cpsie   f
  75   isb
  76   bx      LR
  77
  78 ArmDisableFiq
  79   cpsid   f
  80   isb
  81   bx      LR
  82
  83 ArmEnableInterrupts
  84   cpsie   if
  85   isb
  86   bx      LR
  87
  88 ArmDisableInterrupts
  89   cpsid   if
  90   isb
  91   bx      LR
  92
  93 // UINT32
  94 // ReadCCSIDR (
  95 //   IN UINT32 CSSELR
  96 //   )
  97 ReadCCSIDR
  98   mcr p15,2,r0,c0,c0,0   ; Write Cache Size Selection Register (CSSELR)
  99   isb
 100   mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
 101   bx  lr
 102
 103 // UINT32
 104 // ReadCLIDR (
 105 //   IN UINT32 CSSELR
 106 //   )
 107 ReadCLIDR
 108   mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
 109   bx  lr
 110
 111 ArmReadNsacr
 112   mrc     p15, 0, r0, c1, c1, 2
 113   bx      lr
 114
 115 ArmWriteNsacr
 116   mcr     p15, 0, r0, c1, c1, 2
 117   bx      lr
 118
 119   END