ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
   4 // Copyright (c) 2011-2013, ARM Limited. All rights reserved.
   5 //
   6 // This program and the accompanying materials
   7 // are licensed and made available under the terms and conditions of the BSD License
   8 // which accompanies this distribution.  The full text of the license may be found at
   9 // http://opensource.org/licenses/bsd-license.php
  10 //
  11 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 //
  14 //------------------------------------------------------------------------------
  15
  16
  17
  18     INCLUDE AsmMacroExport.inc
  19
  20
  21 //------------------------------------------------------------------------------
  22
  23  RVCT_ASM_EXPORT ArmIsMpCore
  24   mrc     p15,0,R0,c0,c0,5
  25   // Get Multiprocessing extension (bit31) & U bit (bit30)
  26   and     R0, R0, #0xC0000000
  27   // if (bit31 == 1) && (bit30 == 0) then the processor is part of a multiprocessor system
  28   cmp     R0, #0x80000000
  29   moveq   R0, #1
  30   movne   R0, #0
  31   bx      LR
  32
  33  RVCT_ASM_EXPORT ArmEnableAsynchronousAbort
  34   cpsie   a
  35   isb
  36   bx      LR
  37
  38  RVCT_ASM_EXPORT ArmDisableAsynchronousAbort
  39   cpsid   a
  40   isb
  41   bx      LR
  42
  43  RVCT_ASM_EXPORT ArmEnableIrq
  44   cpsie   i
  45   isb
  46   bx      LR
  47
  48  RVCT_ASM_EXPORT ArmDisableIrq
  49   cpsid   i
  50   isb
  51   bx      LR
  52
  53  RVCT_ASM_EXPORT ArmEnableFiq
  54   cpsie   f
  55   isb
  56   bx      LR
  57
  58  RVCT_ASM_EXPORT ArmDisableFiq
  59   cpsid   f
  60   isb
  61   bx      LR
  62
  63  RVCT_ASM_EXPORT ArmEnableInterrupts
  64   cpsie   if
  65   isb
  66   bx      LR
  67
  68  RVCT_ASM_EXPORT ArmDisableInterrupts
  69   cpsid   if
  70   isb
  71   bx      LR
  72
  73 // UINT32
  74 // ReadCCSIDR (
  75 //   IN UINT32 CSSELR
  76 //   )
  77  RVCT_ASM_EXPORT ReadCCSIDR
  78   mcr p15,2,r0,c0,c0,0   ; Write Cache Size Selection Register (CSSELR)
  79   isb
  80   mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
  81   bx  lr
  82
  83 // UINT32
  84 // ReadCLIDR (
  85 //   IN UINT32 CSSELR
  86 //   )
  87  RVCT_ASM_EXPORT ReadCLIDR
  88   mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
  89   bx  lr
  90
  91  RVCT_ASM_EXPORT ArmReadNsacr
  92   mrc     p15, 0, r0, c1, c1, 2
  93   bx      lr
  94
  95  RVCT_ASM_EXPORT ArmWriteNsacr
  96   mcr     p15, 0, r0, c1, c1, 2
  97   bx      lr
  98
  99   END