1 #------------------------------------------------------------------------------
3 # Copyright (c) 2008-2009 Apple Inc. All rights reserved.
5 # All rights reserved. This program and the accompanying materials
6 # are licensed and made available under the terms and conditions of the BSD License
7 # which accompanies this distribution. The full text of the license may be found at
8 # http://opensource.org/licenses/bsd-license.php
10 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 #------------------------------------------------------------------------------
17 .globl ASM_PFX(ArmInvalidateInstructionCache)
18 .globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
19 .globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
20 .globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA)
21 .globl ASM_PFX(ArmInvalidateDataCacheEntryBySetWay)
22 .globl ASM_PFX(ArmCleanDataCacheEntryBySetWay)
23 .globl ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay)
24 .globl ASM_PFX(ArmDrainWriteBuffer)
25 .globl ASM_PFX(ArmEnableMmu)
26 .globl ASM_PFX(ArmDisableMmu)
27 .globl ASM_PFX(ArmMmuEnabled)
28 .globl ASM_PFX(ArmEnableDataCache)
29 .globl ASM_PFX(ArmDisableDataCache)
30 .globl ASM_PFX(ArmEnableInstructionCache)
31 .globl ASM_PFX(ArmDisableInstructionCache)
32 .globl ASM_PFX(ArmEnableExtendPTConfig)
33 .globl ASM_PFX(ArmDisableExtendPTConfig)
34 .globl ASM_PFX(ArmEnableBranchPrediction)
35 .globl ASM_PFX(ArmDisableBranchPrediction)
36 .globl ASM_PFX(ArmV7AllDataCachesOperation)
42 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
43 mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
49 ASM_PFX(ArmCleanDataCacheEntryByMVA):
50 mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
56 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
57 mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
63 ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
64 mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line
70 ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
71 mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line
77 ASM_PFX(ArmCleanDataCacheEntryBySetWay):
78 mcr p15, 0, r0, c7, c10, 2 @ Clean this line
84 ASM_PFX(ArmDrainWriteBuffer):
85 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer for sync
91 ASM_PFX(ArmInvalidateInstructionCache):
93 mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache
99 ASM_PFX(ArmEnableMmu):
105 ASM_PFX(ArmMmuEnabled):
111 ASM_PFX(ArmDisableMmu):
113 mcr p15,0,R0,c13,c0,0 @FCSE PID register must be cleared before disabling MMU
116 mcr p15,0,R0,c1,c0,0 @Disable MMU
122 ASM_PFX(ArmEnableDataCache):
124 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
125 orr R0,R0,R1 @Set C bit
126 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
131 ASM_PFX(ArmDisableDataCache):
133 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
134 bic R0,R0,R1 @Clear C bit
135 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
140 ASM_PFX(ArmEnableInstructionCache):
142 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
143 orr R0,R0,R1 @Set I bit
144 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
149 ASM_PFX(ArmDisableInstructionCache):
151 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
152 bic R0,R0,R1 @Clear I bit.
153 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
158 ASM_PFX(ArmEnableBranchPrediction):
159 mrc p15, 0, r0, c1, c0, 0
160 orr r0, r0, #0x00000800
161 mcr p15, 0, r0, c1, c0, 0
166 ASM_PFX(ArmDisableBranchPrediction):
167 mrc p15, 0, r0, c1, c0, 0
168 bic r0, r0, #0x00000800
169 mcr p15, 0, r0, c1, c0, 0
175 ASM_PFX(ArmV7AllDataCachesOperation):
176 stmfd SP!,{r4-r12, LR}
177 mov R1, R0 @ Save Function call in R1
178 mrc p15, 1, R6, c0, c0, 1 @ Read CLIDR
179 ands R3, R6, #0x7000000 @ Mask out all but Level of Coherency (LoC)
180 mov R3, R3, LSR #23 @ Cache level value (naturally aligned)
185 add R2, R10, R10, LSR #1 @ Work out 3xcachelevel
186 mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level
187 and R12, R12, #7 @ get those 3 bits alone
189 blt L_Skip @ no cache or only instruction cache at this level
190 mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
191 isb @ ISB to sync the change to the CacheSizeID reg
192 mcr p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)
193 and R2, R12, #0x7 @ extract the line length field
194 and R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes)
197 ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned)
198 clz R5, R4 @ R5 is the bit position of the way size increment
201 ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned)
204 mov R9, R4 @ R9 working copy of the max way size (right aligned)
207 orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11
208 orr R0, R0, R7, LSL R2 @ factor in the index number
212 subs R9, R9, #1 @ decrement the way number
214 subs R7, R7, #1 @ decrement the index
217 add R10, R10, #2 @ increment the cache number
222 ldmfd SP!, {r4-r12, lr}
226 ASM_FUNCTION_REMOVE_IF_UNREFERENCED