ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
   5 #
   6 # This program and the accompanying materials
   7 # are licensed and made available under the terms and conditions of the BSD License
   8 # which accompanies this distribution.  The full text of the license may be found at
   9 # http://opensource.org/licenses/bsd-license.php
  10 #
  11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 #
  14 #------------------------------------------------------------------------------
  15
  16 .text
  17 .align 2
  18
  19 GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
  20 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
  21 GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
  22 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
  23 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
  24 GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
  25 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)
  26 GCC_ASM_EXPORT (ArmDrainWriteBuffer)
  27 GCC_ASM_EXPORT (ArmEnableMmu)
  28 GCC_ASM_EXPORT (ArmDisableMmu)
  29 GCC_ASM_EXPORT (ArmDisableCachesAndMmu)
  30 GCC_ASM_EXPORT (ArmMmuEnabled)
  31 GCC_ASM_EXPORT (ArmEnableDataCache)
  32 GCC_ASM_EXPORT (ArmDisableDataCache)
  33 GCC_ASM_EXPORT (ArmEnableInstructionCache)
  34 GCC_ASM_EXPORT (ArmDisableInstructionCache)
  35 GCC_ASM_EXPORT (ArmEnableSWPInstruction)
  36 GCC_ASM_EXPORT (ArmEnableBranchPrediction)
  37 GCC_ASM_EXPORT (ArmDisableBranchPrediction)
  38 GCC_ASM_EXPORT (ArmSetLowVectors)
  39 GCC_ASM_EXPORT (ArmSetHighVectors)
  40 GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)
  41 GCC_ASM_EXPORT (ArmV7PerformPoUDataCacheOperation)
  42 GCC_ASM_EXPORT (ArmDataMemoryBarrier)
  43 GCC_ASM_EXPORT (ArmDataSyncronizationBarrier)
  44 GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
  45 GCC_ASM_EXPORT (ArmReadVBar)
  46 GCC_ASM_EXPORT (ArmWriteVBar)
  47 GCC_ASM_EXPORT (ArmEnableVFP)
  48 GCC_ASM_EXPORT (ArmCallWFI)
  49 GCC_ASM_EXPORT (ArmReadCbar)
  50 GCC_ASM_EXPORT (ArmReadMpidr)
  51 GCC_ASM_EXPORT (ArmReadTpidrurw)
  52 GCC_ASM_EXPORT (ArmWriteTpidrurw)
  53 GCC_ASM_EXPORT (ArmIsArchTimerImplemented)
  54 GCC_ASM_EXPORT (ArmReadIdPfr1)
  55
  56 .set DC_ON, (0x1<<2)
  57 .set IC_ON, (0x1<<12)
  58 .set CTRL_M_BIT,  (1 << 0)
  59 .set CTRL_C_BIT,  (1 << 2)
  60 .set CTRL_B_BIT,  (1 << 7)
  61 .set CTRL_I_BIT,  (1 << 12)
  62
  63
  64 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
  65   mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line
  66   dsb
  67   isb
  68   bx      lr
  69
  70 ASM_PFX(ArmCleanDataCacheEntryByMVA):
  71   mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line
  72   dsb
  73   isb
  74   bx      lr
  75
  76
  77 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
  78   mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line
  79   dsb
  80   isb
  81   bx      lr
  82
  83
  84 ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
  85   mcr     p15, 0, r0, c7, c6, 2        @ Invalidate this line
  86   dsb
  87   isb
  88   bx      lr
  89
  90
  91 ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
  92   mcr     p15, 0, r0, c7, c14, 2       @ Clean and Invalidate this line
  93   dsb
  94   isb
  95   bx      lr
  96
  97
  98 ASM_PFX(ArmCleanDataCacheEntryBySetWay):
  99   mcr     p15, 0, r0, c7, c10, 2       @ Clean this line
 100   dsb
 101   isb
 102   bx      lr
 103
 104 ASM_PFX(ArmInvalidateInstructionCache):
 105   mcr     p15,0,R0,c7,c5,0      @Invalidate entire instruction cache
 106   dsb
 107   isb
 108   bx      LR
 109
 110 ASM_PFX(ArmEnableMmu):
 111   mrc     p15,0,R0,c1,c0,0
 112   orr     R0,R0,#1
 113   mcr     p15,0,R0,c1,c0,0
 114   dsb
 115   isb
 116   bx      LR
 117
 118
 119 ASM_PFX(ArmDisableMmu):
 120   mrc     p15,0,R0,c1,c0,0
 121   bic     R0,R0,#1
 122   mcr     p15,0,R0,c1,c0,0      @Disable MMU
 123
 124   mcr     p15,0,R0,c8,c7,0      @Invalidate TLB
 125   mcr     p15,0,R0,c7,c5,6      @Invalidate Branch predictor array
 126   dsb
 127   isb
 128   bx      LR
 129
 130 ASM_PFX(ArmDisableCachesAndMmu):
 131   mrc   p15, 0, r0, c1, c0, 0           @ Get control register
 132   bic   r0, r0, #CTRL_M_BIT             @ Disable MMU
 133   bic   r0, r0, #CTRL_C_BIT             @ Disable D Cache
 134   bic   r0, r0, #CTRL_I_BIT             @ Disable I Cache
 135   mcr   p15, 0, r0, c1, c0, 0           @ Write control register
 136   dsb
 137   isb
 138   bx      LR
 139
 140 ASM_PFX(ArmMmuEnabled):
 141   mrc     p15,0,R0,c1,c0,0
 142   and     R0,R0,#1
 143   bx      LR
 144
 145 ASM_PFX(ArmEnableDataCache):
 146   ldr     R1,=DC_ON
 147   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 148   orr     R0,R0,R1              @Set C bit
 149   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 150   dsb
 151   isb
 152   bx      LR
 153
 154 ASM_PFX(ArmDisableDataCache):
 155   ldr     R1,=DC_ON
 156   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 157   bic     R0,R0,R1              @Clear C bit
 158   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 159   dsb
 160   isb
 161   bx      LR
 162
 163 ASM_PFX(ArmEnableInstructionCache):
 164   ldr     R1,=IC_ON
 165   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 166   orr     R0,R0,R1              @Set I bit
 167   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 168   dsb
 169   isb
 170   bx      LR
 171
 172 ASM_PFX(ArmDisableInstructionCache):
 173   ldr     R1,=IC_ON
 174   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 175   bic     R0,R0,R1              @Clear I bit.
 176   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 177   dsb
 178   isb
 179   bx      LR
 180
 181 ASM_PFX(ArmEnableSWPInstruction):
 182   mrc     p15, 0, r0, c1, c0, 0
 183   orr     r0, r0, #0x00000400
 184   mcr     p15, 0, r0, c1, c0, 0
 185   isb
 186   bx      LR
 187
 188 ASM_PFX(ArmEnableBranchPrediction):
 189   mrc     p15, 0, r0, c1, c0, 0
 190   orr     r0, r0, #0x00000800
 191   mcr     p15, 0, r0, c1, c0, 0
 192   dsb
 193   isb
 194   bx      LR
 195
 196 ASM_PFX(ArmDisableBranchPrediction):
 197   mrc     p15, 0, r0, c1, c0, 0
 198   bic     r0, r0, #0x00000800
 199   mcr     p15, 0, r0, c1, c0, 0
 200   dsb
 201   isb
 202   bx      LR
 203
 204 ASM_PFX(ArmSetLowVectors):
 205   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 206   bic     r0, r0, #0x00002000   @ clear V bit
 207   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 208   isb
 209   bx      LR
 210
 211 ASM_PFX(ArmSetHighVectors):
 212   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 213   orr     r0, r0, #0x00002000   @ Set V bit
 214   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 215   isb
 216   bx      LR
 217
 218 ASM_PFX(ArmV7AllDataCachesOperation):
 219   stmfd SP!,{r4-r12, LR}
 220   mov   R1, R0                @ Save Function call in R1
 221   mrc   p15, 1, R6, c0, c0, 1 @ Read CLIDR
 222   ands  R3, R6, #0x7000000    @ Mask out all but Level of Coherency (LoC)
 223   mov   R3, R3, LSR #23       @ Cache level value (naturally aligned)
 224   beq   L_Finished
 225   mov   R10, #0
 226
 227 Loop1:
 228   add   R2, R10, R10, LSR #1  @ Work out 3xcachelevel
 229   mov   R12, R6, LSR R2       @ bottom 3 bits are the Cache type for this level
 230   and   R12, R12, #7          @ get those 3 bits alone
 231   cmp   R12, #2
 232   blt   L_Skip                  @ no cache or only instruction cache at this level
 233   mcr   p15, 2, R10, c0, c0, 0  @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
 234   isb                           @ isb to sync the change to the CacheSizeID reg
 235   mrc   p15, 1, R12, c0, c0, 0  @ reads current Cache Size ID register (CCSIDR)
 236   and   R2, R12, #0x7           @ extract the line length field
 237   add   R2, R2, #4              @ add 4 for the line length offset (log2 16 bytes)
 238 @  ldr   R4, =0x3FF
 239   mov   R4, #0x400
 240   sub   R4, R4, #1
 241   ands  R4, R4, R12, LSR #3     @ R4 is the max number on the way size (right aligned)
 242   clz   R5, R4                  @ R5 is the bit position of the way size increment
 243 @  ldr   R7, =0x00007FFF
 244   mov   R7, #0x00008000
 245   sub   R7, R7, #1
 246   ands  R7, R7, R12, LSR #13    @ R7 is the max number of the index size (right aligned)
 247
 248 Loop2:
 249   mov   R9, R4                  @ R9 working copy of the max way size (right aligned)
 250
 251 Loop3:
 252   orr   R0, R10, R9, LSL R5     @ factor in the way number and cache number into R11
 253   orr   R0, R0, R7, LSL R2      @ factor in the index number
 254
 255   blx   R1
 256
 257   subs  R9, R9, #1              @ decrement the way number
 258   bge   Loop3
 259   subs  R7, R7, #1              @ decrement the index
 260   bge   Loop2
 261 L_Skip:
 262   add   R10, R10, #2            @ increment the cache number
 263   cmp   R3, R10
 264   bgt   Loop1
 265
 266 L_Finished:
 267   dsb
 268   ldmfd SP!, {r4-r12, lr}
 269   bx    LR
 270
 271 ASM_PFX(ArmV7PerformPoUDataCacheOperation):
 272   stmfd SP!,{r4-r12, LR}
 273   mov   R1, R0                @ Save Function call in R1
 274   mrc   p15, 1, R6, c0, c0, 1 @ Read CLIDR
 275   ands  R3, R6, #0x38000000    @ Mask out all but Level of Unification (LoU)
 276   mov   R3, R3, LSR #26       @ Cache level value (naturally aligned)
 277   beq   Finished2
 278   mov   R10, #0
 279
 280 Loop4:
 281   add   R2, R10, R10, LSR #1    @ Work out 3xcachelevel
 282   mov   R12, R6, LSR R2         @ bottom 3 bits are the Cache type for this level
 283   and   R12, R12, #7            @ get those 3 bits alone
 284   cmp   R12, #2
 285   blt   Skip2                   @ no cache or only instruction cache at this level
 286   mcr   p15, 2, R10, c0, c0, 0  @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
 287   isb                           @ isb to sync the change to the CacheSizeID reg
 288   mrc   p15, 1, R12, c0, c0, 0  @ reads current Cache Size ID register (CCSIDR)
 289   and   R2, R12, #0x7            @ extract the line length field
 290   add   R2, R2, #4              @ add 4 for the line length offset (log2 16 bytes)
 291   ldr   R4, =0x3FF
 292   ands  R4, R4, R12, LSR #3     @ R4 is the max number on the way size (right aligned)
 293   clz   R5, R4                  @ R5 is the bit position of the way size increment
 294   ldr   R7, =0x00007FFF
 295   ands  R7, R7, R12, LSR #13    @ R7 is the max number of the index size (right aligned)
 296
 297 Loop5:
 298   mov   R9, R4                  @ R9 working copy of the max way size (right aligned)
 299
 300 Loop6:
 301   orr   R0, R10, R9, LSL R5     @ factor in the way number and cache number into R11
 302   orr   R0, R0, R7, LSL R2      @ factor in the index number
 303
 304   blx   R1
 305
 306   subs  R9, R9, #1              @ decrement the way number
 307   bge   Loop6
 308   subs  R7, R7, #1              @ decrement the index
 309   bge   Loop5
 310 Skip2:
 311   add   R10, R10, #2            @ increment the cache number
 312   cmp   R3, R10
 313   bgt   Loop4
 314
 315 Finished2:
 316   dsb
 317   ldmfd SP!, {r4-r12, lr}
 318   bx    LR
 319
 320 ASM_PFX(ArmDataMemoryBarrier):
 321   dmb
 322   bx      LR
 323
 324 ASM_PFX(ArmDataSyncronizationBarrier):
 325 ASM_PFX(ArmDrainWriteBuffer):
 326   dsb
 327   bx      LR
 328
 329 ASM_PFX(ArmInstructionSynchronizationBarrier):
 330   isb
 331   bx      LR
 332
 333 ASM_PFX(ArmReadVBar):
 334   # Set the Address of the Vector Table in the VBAR register
 335   mrc     p15, 0, r0, c12, c0, 0
 336   bx      lr
 337
 338 ASM_PFX(ArmWriteVBar):
 339   # Set the Address of the Vector Table in the VBAR register
 340   mcr     p15, 0, r0, c12, c0, 0
 341   # Ensure the SCTLR.V bit is clear
 342   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 343   bic     r0, r0, #0x00002000   @ clear V bit
 344   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 345   isb
 346   bx      lr
 347
 348 ASM_PFX(ArmEnableVFP):
 349   # Read CPACR (Coprocessor Access Control Register)
 350   mrc     p15, 0, r0, c1, c0, 2
 351   # Enable VPF access (Full Access to CP10, CP11) (V* instructions)
 352   orr     r0, r0, #0x00f00000
 353   # Write back CPACR (Coprocessor Access Control Register)
 354   mcr     p15, 0, r0, c1, c0, 2
 355   isb
 356   # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
 357   mov     r0, #0x40000000
 358   mcr     p10,#0x7,r0,c8,c0,#0
 359   bx      lr
 360
 361 ASM_PFX(ArmCallWFI):
 362   wfi
 363   bx      lr
 364
 365 #Note: Return 0 in Uniprocessor implementation
 366 ASM_PFX(ArmReadCbar):
 367   mrc     p15, 4, r0, c15, c0, 0  @ Read Configuration Base Address Register
 368   bx      lr
 369
 370 ASM_PFX(ArmReadMpidr):
 371   mrc     p15, 0, r0, c0, c0, 5       @ read MPIDR
 372   bx      lr
 373
 374 ASM_PFX(ArmReadTpidrurw):
 375   mrc     p15, 0, r0, c13, c0, 2    @ read TPIDRURW
 376   bx      lr
 377
 378 ASM_PFX(ArmWriteTpidrurw):
 379   mcr     p15, 0, r0, c13, c0, 2    @ write TPIDRURW
 380   bx      lr
 381
 382 ASM_PFX(ArmIsArchTimerImplemented):
 383   mrc    p15, 0, r0, c0, c1, 1     @ Read ID_PFR1
 384   and    r0, r0, #0x000F0000
 385   bx     lr
 386
 387 ASM_PFX(ArmReadIdPfr1):
 388   mrc    p15, 0, r0, c0, c1, 1     @ Read ID_PFR1 Register
 389   bx     lr
 390
 391 ASM_FUNCTION_REMOVE_IF_UNREFERENCED