ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
   5 #
   6 # This program and the accompanying materials
   7 # are licensed and made available under the terms and conditions of the BSD License
   8 # which accompanies this distribution.  The full text of the license may be found at
   9 # http://opensource.org/licenses/bsd-license.php
  10 #
  11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 #
  14 #------------------------------------------------------------------------------
  15
  16 .text
  17 .align 2
  18
  19 GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
  20 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
  21 GCC_ASM_EXPORT (ArmInvalidateInstructionCacheEntryToPoUByMVA)
  22 GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
  23 GCC_ASM_EXPORT (ArmCleanDataCacheEntryToPoUByMVA)
  24 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
  25 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
  26 GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
  27 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)
  28 GCC_ASM_EXPORT (ArmEnableMmu)
  29 GCC_ASM_EXPORT (ArmDisableMmu)
  30 GCC_ASM_EXPORT (ArmDisableCachesAndMmu)
  31 GCC_ASM_EXPORT (ArmMmuEnabled)
  32 GCC_ASM_EXPORT (ArmEnableDataCache)
  33 GCC_ASM_EXPORT (ArmDisableDataCache)
  34 GCC_ASM_EXPORT (ArmEnableInstructionCache)
  35 GCC_ASM_EXPORT (ArmDisableInstructionCache)
  36 GCC_ASM_EXPORT (ArmEnableSWPInstruction)
  37 GCC_ASM_EXPORT (ArmEnableBranchPrediction)
  38 GCC_ASM_EXPORT (ArmDisableBranchPrediction)
  39 GCC_ASM_EXPORT (ArmSetLowVectors)
  40 GCC_ASM_EXPORT (ArmSetHighVectors)
  41 GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)
  42 GCC_ASM_EXPORT (ArmDataMemoryBarrier)
  43 GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)
  44 GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
  45 GCC_ASM_EXPORT (ArmReadVBar)
  46 GCC_ASM_EXPORT (ArmWriteVBar)
  47 GCC_ASM_EXPORT (ArmEnableVFP)
  48 GCC_ASM_EXPORT (ArmCallWFI)
  49 GCC_ASM_EXPORT (ArmReadCbar)
  50 GCC_ASM_EXPORT (ArmReadMpidr)
  51 GCC_ASM_EXPORT (ArmReadTpidrurw)
  52 GCC_ASM_EXPORT (ArmWriteTpidrurw)
  53 GCC_ASM_EXPORT (ArmIsArchTimerImplemented)
  54 GCC_ASM_EXPORT (ArmReadIdPfr1)
  55 GCC_ASM_EXPORT (ArmReadIdMmfr0)
  56
  57 .set DC_ON, (0x1<<2)
  58 .set IC_ON, (0x1<<12)
  59 .set CTRL_M_BIT,  (1 << 0)
  60 .set CTRL_C_BIT,  (1 << 2)
  61 .set CTRL_B_BIT,  (1 << 7)
  62 .set CTRL_I_BIT,  (1 << 12)
  63
  64
  65 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
  66   mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line
  67   bx      lr
  68
  69 ASM_PFX(ArmCleanDataCacheEntryByMVA):
  70   mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line
  71   bx      lr
  72
  73
  74 ASM_PFX(ArmCleanDataCacheEntryToPoUByMVA):
  75   mcr     p15, 0, r0, c7, c11, 1  @clean single data cache line to PoU
  76   bx      lr
  77
  78 ASM_PFX(ArmInvalidateInstructionCacheEntryToPoUByMVA):
  79   mcr     p15, 0, r0, c7, c5, 1  @Invalidate single instruction cache line to PoU
  80   mcr     p15, 0, r0, c7, c5, 7  @Invalidate branch predictor
  81   bx      lr
  82
  83 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
  84   mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line
  85   bx      lr
  86
  87
  88 ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
  89   mcr     p15, 0, r0, c7, c6, 2        @ Invalidate this line
  90   bx      lr
  91
  92
  93 ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
  94   mcr     p15, 0, r0, c7, c14, 2       @ Clean and Invalidate this line
  95   bx      lr
  96
  97
  98 ASM_PFX(ArmCleanDataCacheEntryBySetWay):
  99   mcr     p15, 0, r0, c7, c10, 2       @ Clean this line
 100   bx      lr
 101
 102 ASM_PFX(ArmInvalidateInstructionCache):
 103   mcr     p15,0,R0,c7,c5,0      @Invalidate entire instruction cache
 104   dsb
 105   isb
 106   bx      LR
 107
 108 ASM_PFX(ArmEnableMmu):
 109   mrc     p15,0,R0,c1,c0,0
 110   orr     R0,R0,#1
 111   mcr     p15,0,R0,c1,c0,0
 112   dsb
 113   isb
 114   bx      LR
 115
 116
 117 ASM_PFX(ArmDisableMmu):
 118   mrc     p15,0,R0,c1,c0,0
 119   bic     R0,R0,#1
 120   mcr     p15,0,R0,c1,c0,0      @Disable MMU
 121
 122   mcr     p15,0,R0,c8,c7,0      @Invalidate TLB
 123   mcr     p15,0,R0,c7,c5,6      @Invalidate Branch predictor array
 124   dsb
 125   isb
 126   bx      LR
 127
 128 ASM_PFX(ArmDisableCachesAndMmu):
 129   mrc   p15, 0, r0, c1, c0, 0           @ Get control register
 130   bic   r0, r0, #CTRL_M_BIT             @ Disable MMU
 131   bic   r0, r0, #CTRL_C_BIT             @ Disable D Cache
 132   bic   r0, r0, #CTRL_I_BIT             @ Disable I Cache
 133   mcr   p15, 0, r0, c1, c0, 0           @ Write control register
 134   dsb
 135   isb
 136   bx      LR
 137
 138 ASM_PFX(ArmMmuEnabled):
 139   mrc     p15,0,R0,c1,c0,0
 140   and     R0,R0,#1
 141   bx      LR
 142
 143 ASM_PFX(ArmEnableDataCache):
 144   ldr     R1,=DC_ON
 145   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 146   orr     R0,R0,R1              @Set C bit
 147   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 148   dsb
 149   isb
 150   bx      LR
 151
 152 ASM_PFX(ArmDisableDataCache):
 153   ldr     R1,=DC_ON
 154   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 155   bic     R0,R0,R1              @Clear C bit
 156   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 157   dsb
 158   isb
 159   bx      LR
 160
 161 ASM_PFX(ArmEnableInstructionCache):
 162   ldr     R1,=IC_ON
 163   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 164   orr     R0,R0,R1              @Set I bit
 165   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 166   dsb
 167   isb
 168   bx      LR
 169
 170 ASM_PFX(ArmDisableInstructionCache):
 171   ldr     R1,=IC_ON
 172   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 173   bic     R0,R0,R1              @Clear I bit.
 174   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 175   dsb
 176   isb
 177   bx      LR
 178
 179 ASM_PFX(ArmEnableSWPInstruction):
 180   mrc     p15, 0, r0, c1, c0, 0
 181   orr     r0, r0, #0x00000400
 182   mcr     p15, 0, r0, c1, c0, 0
 183   isb
 184   bx      LR
 185
 186 ASM_PFX(ArmEnableBranchPrediction):
 187   mrc     p15, 0, r0, c1, c0, 0
 188   orr     r0, r0, #0x00000800
 189   mcr     p15, 0, r0, c1, c0, 0
 190   dsb
 191   isb
 192   bx      LR
 193
 194 ASM_PFX(ArmDisableBranchPrediction):
 195   mrc     p15, 0, r0, c1, c0, 0
 196   bic     r0, r0, #0x00000800
 197   mcr     p15, 0, r0, c1, c0, 0
 198   dsb
 199   isb
 200   bx      LR
 201
 202 ASM_PFX(ArmSetLowVectors):
 203   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 204   bic     r0, r0, #0x00002000   @ clear V bit
 205   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 206   isb
 207   bx      LR
 208
 209 ASM_PFX(ArmSetHighVectors):
 210   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 211   orr     r0, r0, #0x00002000   @ Set V bit
 212   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 213   isb
 214   bx      LR
 215
 216 ASM_PFX(ArmV7AllDataCachesOperation):
 217   stmfd SP!,{r4-r12, LR}
 218   mov   R1, R0                @ Save Function call in R1
 219   mrc   p15, 1, R6, c0, c0, 1 @ Read CLIDR
 220   ands  R3, R6, #0x7000000    @ Mask out all but Level of Coherency (LoC)
 221   mov   R3, R3, LSR #23       @ Cache level value (naturally aligned)
 222   beq   L_Finished
 223   mov   R10, #0
 224
 225 Loop1:
 226   add   R2, R10, R10, LSR #1  @ Work out 3xcachelevel
 227   mov   R12, R6, LSR R2       @ bottom 3 bits are the Cache type for this level
 228   and   R12, R12, #7          @ get those 3 bits alone
 229   cmp   R12, #2
 230   blt   L_Skip                  @ no cache or only instruction cache at this level
 231   mcr   p15, 2, R10, c0, c0, 0  @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
 232   isb                           @ isb to sync the change to the CacheSizeID reg
 233   mrc   p15, 1, R12, c0, c0, 0  @ reads current Cache Size ID register (CCSIDR)
 234   and   R2, R12, #0x7           @ extract the line length field
 235   add   R2, R2, #4              @ add 4 for the line length offset (log2 16 bytes)
 236 @  ldr   R4, =0x3FF
 237   mov   R4, #0x400
 238   sub   R4, R4, #1
 239   ands  R4, R4, R12, LSR #3     @ R4 is the max number on the way size (right aligned)
 240   clz   R5, R4                  @ R5 is the bit position of the way size increment
 241 @  ldr   R7, =0x00007FFF
 242   mov   R7, #0x00008000
 243   sub   R7, R7, #1
 244   ands  R7, R7, R12, LSR #13    @ R7 is the max number of the index size (right aligned)
 245
 246 Loop2:
 247   mov   R9, R4                  @ R9 working copy of the max way size (right aligned)
 248
 249 Loop3:
 250   orr   R0, R10, R9, LSL R5     @ factor in the way number and cache number into R11
 251   orr   R0, R0, R7, LSL R2      @ factor in the index number
 252
 253   blx   R1
 254
 255   subs  R9, R9, #1              @ decrement the way number
 256   bge   Loop3
 257   subs  R7, R7, #1              @ decrement the index
 258   bge   Loop2
 259 L_Skip:
 260   add   R10, R10, #2            @ increment the cache number
 261   cmp   R3, R10
 262   bgt   Loop1
 263
 264 L_Finished:
 265   dsb
 266   ldmfd SP!, {r4-r12, lr}
 267   bx    LR
 268
 269 ASM_PFX(ArmDataMemoryBarrier):
 270   dmb
 271   bx      LR
 272
 273 ASM_PFX(ArmDataSynchronizationBarrier):
 274   dsb
 275   bx      LR
 276
 277 ASM_PFX(ArmInstructionSynchronizationBarrier):
 278   isb
 279   bx      LR
 280
 281 ASM_PFX(ArmReadVBar):
 282   # Set the Address of the Vector Table in the VBAR register
 283   mrc     p15, 0, r0, c12, c0, 0
 284   bx      lr
 285
 286 ASM_PFX(ArmWriteVBar):
 287   # Set the Address of the Vector Table in the VBAR register
 288   mcr     p15, 0, r0, c12, c0, 0
 289   # Ensure the SCTLR.V bit is clear
 290   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 291   bic     r0, r0, #0x00002000   @ clear V bit
 292   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 293   isb
 294   bx      lr
 295
 296 ASM_PFX(ArmEnableVFP):
 297   # Read CPACR (Coprocessor Access Control Register)
 298   mrc     p15, 0, r0, c1, c0, 2
 299   # Enable VPF access (Full Access to CP10, CP11) (V* instructions)
 300   orr     r0, r0, #0x00f00000
 301   # Write back CPACR (Coprocessor Access Control Register)
 302   mcr     p15, 0, r0, c1, c0, 2
 303   isb
 304   # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
 305   mov     r0, #0x40000000
 306 #ifndef __clang__
 307   mcr     p10,#0x7,r0,c8,c0,#0
 308 #else
 309   vmsr    fpexc, r0
 310 #endif
 311   bx      lr
 312
 313 ASM_PFX(ArmCallWFI):
 314   wfi
 315   bx      lr
 316
 317 #Note: Return 0 in Uniprocessor implementation
 318 ASM_PFX(ArmReadCbar):
 319   mrc     p15, 4, r0, c15, c0, 0  @ Read Configuration Base Address Register
 320   bx      lr
 321
 322 ASM_PFX(ArmReadMpidr):
 323   mrc     p15, 0, r0, c0, c0, 5       @ read MPIDR
 324   bx      lr
 325
 326 ASM_PFX(ArmReadTpidrurw):
 327   mrc     p15, 0, r0, c13, c0, 2    @ read TPIDRURW
 328   bx      lr
 329
 330 ASM_PFX(ArmWriteTpidrurw):
 331   mcr     p15, 0, r0, c13, c0, 2    @ write TPIDRURW
 332   bx      lr
 333
 334 ASM_PFX(ArmIsArchTimerImplemented):
 335   mrc    p15, 0, r0, c0, c1, 1     @ Read ID_PFR1
 336   and    r0, r0, #0x000F0000
 337   bx     lr
 338
 339 ASM_PFX(ArmReadIdPfr1):
 340   mrc    p15, 0, r0, c0, c1, 1     @ Read ID_PFR1 Register
 341   bx     lr
 342
 343 ASM_PFX(ArmReadIdMmfr0):
 344   mrc    p15, 0, r0, c0, c1, 4     @ Read ID_MMFR0 Register
 345   bx     lr
 346
 347 ASM_FUNCTION_REMOVE_IF_UNREFERENCED