ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
   5 #
   6 # This program and the accompanying materials
   7 # are licensed and made available under the terms and conditions of the BSD License
   8 # which accompanies this distribution.  The full text of the license may be found at
   9 # http://opensource.org/licenses/bsd-license.php
  10 #
  11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 #
  14 #------------------------------------------------------------------------------
  15
  16 .text
  17 .align 2
  18
  19 GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
  20 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
  21 GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
  22 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
  23 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
  24 GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
  25 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)
  26 GCC_ASM_EXPORT (ArmDrainWriteBuffer)
  27 GCC_ASM_EXPORT (ArmEnableMmu)
  28 GCC_ASM_EXPORT (ArmDisableMmu)
  29 GCC_ASM_EXPORT (ArmDisableCachesAndMmu)
  30 GCC_ASM_EXPORT (ArmMmuEnabled)
  31 GCC_ASM_EXPORT (ArmEnableDataCache)
  32 GCC_ASM_EXPORT (ArmDisableDataCache)
  33 GCC_ASM_EXPORT (ArmEnableInstructionCache)
  34 GCC_ASM_EXPORT (ArmDisableInstructionCache)
  35 GCC_ASM_EXPORT (ArmEnableSWPInstruction)
  36 GCC_ASM_EXPORT (ArmEnableBranchPrediction)
  37 GCC_ASM_EXPORT (ArmDisableBranchPrediction)
  38 GCC_ASM_EXPORT (ArmSetLowVectors)
  39 GCC_ASM_EXPORT (ArmSetHighVectors)
  40 GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)
  41 GCC_ASM_EXPORT (ArmV7PerformPoUDataCacheOperation)
  42 GCC_ASM_EXPORT (ArmDataMemoryBarrier)
  43 GCC_ASM_EXPORT (ArmDataSyncronizationBarrier)
  44 GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
  45 GCC_ASM_EXPORT (ArmReadVBar)
  46 GCC_ASM_EXPORT (ArmWriteVBar)
  47 GCC_ASM_EXPORT (ArmEnableVFP)
  48 GCC_ASM_EXPORT (ArmCallWFI)
  49 GCC_ASM_EXPORT (ArmReadCbar)
  50 GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb)
  51 GCC_ASM_EXPORT (ArmReadMpidr)
  52 GCC_ASM_EXPORT (ArmReadMidr)
  53 GCC_ASM_EXPORT (ArmReadTpidrurw)
  54 GCC_ASM_EXPORT (ArmWriteTpidrurw)
  55 GCC_ASM_EXPORT (ArmIsArchTimerImplemented)
  56 GCC_ASM_EXPORT (ArmReadIdPfr1)
  57
  58 .set DC_ON, (0x1<<2)
  59 .set IC_ON, (0x1<<12)
  60 .set CTRL_M_BIT,  (1 << 0)
  61 .set CTRL_C_BIT,  (1 << 2)
  62 .set CTRL_B_BIT,  (1 << 7)
  63 .set CTRL_I_BIT,  (1 << 12)
  64
  65
  66 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
  67   mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line
  68   dsb
  69   isb
  70   bx      lr
  71
  72 ASM_PFX(ArmCleanDataCacheEntryByMVA):
  73   mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line
  74   dsb
  75   isb
  76   bx      lr
  77
  78
  79 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
  80   mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line
  81   dsb
  82   isb
  83   bx      lr
  84
  85
  86 ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
  87   mcr     p15, 0, r0, c7, c6, 2        @ Invalidate this line
  88   dsb
  89   isb
  90   bx      lr
  91
  92
  93 ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
  94   mcr     p15, 0, r0, c7, c14, 2       @ Clean and Invalidate this line
  95   dsb
  96   isb
  97   bx      lr
  98
  99
 100 ASM_PFX(ArmCleanDataCacheEntryBySetWay):
 101   mcr     p15, 0, r0, c7, c10, 2       @ Clean this line
 102   dsb
 103   isb
 104   bx      lr
 105
 106 ASM_PFX(ArmInvalidateInstructionCache):
 107   mcr     p15,0,R0,c7,c5,0      @Invalidate entire instruction cache
 108   dsb
 109   isb
 110   bx      LR
 111
 112 ASM_PFX(ArmEnableMmu):
 113   mrc     p15,0,R0,c1,c0,0
 114   orr     R0,R0,#1
 115   mcr     p15,0,R0,c1,c0,0
 116   dsb
 117   isb
 118   bx      LR
 119
 120
 121 ASM_PFX(ArmDisableMmu):
 122   mrc     p15,0,R0,c1,c0,0
 123   bic     R0,R0,#1
 124   mcr     p15,0,R0,c1,c0,0      @Disable MMU
 125
 126   mcr     p15,0,R0,c8,c7,0      @Invalidate TLB
 127   mcr     p15,0,R0,c7,c5,6      @Invalidate Branch predictor array
 128   dsb
 129   isb
 130   bx      LR
 131
 132 ASM_PFX(ArmDisableCachesAndMmu):
 133   mrc   p15, 0, r0, c1, c0, 0           @ Get control register
 134   bic   r0, r0, #CTRL_M_BIT             @ Disable MMU
 135   bic   r0, r0, #CTRL_C_BIT             @ Disable D Cache
 136   bic   r0, r0, #CTRL_I_BIT             @ Disable I Cache
 137   mcr   p15, 0, r0, c1, c0, 0           @ Write control register
 138   dsb
 139   isb
 140   bx      LR
 141
 142 ASM_PFX(ArmMmuEnabled):
 143   mrc     p15,0,R0,c1,c0,0
 144   and     R0,R0,#1
 145   bx      LR
 146
 147 ASM_PFX(ArmEnableDataCache):
 148   ldr     R1,=DC_ON
 149   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 150   orr     R0,R0,R1              @Set C bit
 151   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 152   dsb
 153   isb
 154   bx      LR
 155
 156 ASM_PFX(ArmDisableDataCache):
 157   ldr     R1,=DC_ON
 158   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 159   bic     R0,R0,R1              @Clear C bit
 160   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 161   dsb
 162   isb
 163   bx      LR
 164
 165 ASM_PFX(ArmEnableInstructionCache):
 166   ldr     R1,=IC_ON
 167   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 168   orr     R0,R0,R1              @Set I bit
 169   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 170   dsb
 171   isb
 172   bx      LR
 173
 174 ASM_PFX(ArmDisableInstructionCache):
 175   ldr     R1,=IC_ON
 176   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 177   bic     R0,R0,R1              @Clear I bit.
 178   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 179   dsb
 180   isb
 181   bx      LR
 182
 183 ASM_PFX(ArmEnableSWPInstruction):
 184   mrc     p15, 0, r0, c1, c0, 0
 185   orr     r0, r0, #0x00000400
 186   mcr     p15, 0, r0, c1, c0, 0
 187   isb
 188   bx      LR
 189
 190 ASM_PFX(ArmEnableBranchPrediction):
 191   mrc     p15, 0, r0, c1, c0, 0
 192   orr     r0, r0, #0x00000800
 193   mcr     p15, 0, r0, c1, c0, 0
 194   dsb
 195   isb
 196   bx      LR
 197
 198 ASM_PFX(ArmDisableBranchPrediction):
 199   mrc     p15, 0, r0, c1, c0, 0
 200   bic     r0, r0, #0x00000800
 201   mcr     p15, 0, r0, c1, c0, 0
 202   dsb
 203   isb
 204   bx      LR
 205
 206 ASM_PFX(ArmSetLowVectors):
 207   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 208   bic     r0, r0, #0x00002000   @ clear V bit
 209   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 210   isb
 211   bx      LR
 212
 213 ASM_PFX(ArmSetHighVectors):
 214   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 215   orr     r0, r0, #0x00002000   @ Set V bit
 216   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 217   isb
 218   bx      LR
 219
 220 ASM_PFX(ArmV7AllDataCachesOperation):
 221   stmfd SP!,{r4-r12, LR}
 222   mov   R1, R0                @ Save Function call in R1
 223   mrc   p15, 1, R6, c0, c0, 1 @ Read CLIDR
 224   ands  R3, R6, #0x7000000    @ Mask out all but Level of Coherency (LoC)
 225   mov   R3, R3, LSR #23       @ Cache level value (naturally aligned)
 226   beq   L_Finished
 227   mov   R10, #0
 228
 229 Loop1:
 230   add   R2, R10, R10, LSR #1  @ Work out 3xcachelevel
 231   mov   R12, R6, LSR R2       @ bottom 3 bits are the Cache type for this level
 232   and   R12, R12, #7          @ get those 3 bits alone
 233   cmp   R12, #2
 234   blt   L_Skip                  @ no cache or only instruction cache at this level
 235   mcr   p15, 2, R10, c0, c0, 0  @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
 236   isb                           @ isb to sync the change to the CacheSizeID reg
 237   mrc   p15, 1, R12, c0, c0, 0  @ reads current Cache Size ID register (CCSIDR)
 238   and   R2, R12, #0x7           @ extract the line length field
 239   add   R2, R2, #4              @ add 4 for the line length offset (log2 16 bytes)
 240 @  ldr   R4, =0x3FF
 241   mov   R4, #0x400
 242   sub   R4, R4, #1
 243   ands  R4, R4, R12, LSR #3     @ R4 is the max number on the way size (right aligned)
 244   clz   R5, R4                  @ R5 is the bit position of the way size increment
 245 @  ldr   R7, =0x00007FFF
 246   mov   R7, #0x00008000
 247   sub   R7, R7, #1
 248   ands  R7, R7, R12, LSR #13    @ R7 is the max number of the index size (right aligned)
 249
 250 Loop2:
 251   mov   R9, R4                  @ R9 working copy of the max way size (right aligned)
 252
 253 Loop3:
 254   orr   R0, R10, R9, LSL R5     @ factor in the way number and cache number into R11
 255   orr   R0, R0, R7, LSL R2      @ factor in the index number
 256
 257   blx   R1
 258
 259   subs  R9, R9, #1              @ decrement the way number
 260   bge   Loop3
 261   subs  R7, R7, #1              @ decrement the index
 262   bge   Loop2
 263 L_Skip:
 264   add   R10, R10, #2            @ increment the cache number
 265   cmp   R3, R10
 266   bgt   Loop1
 267
 268 L_Finished:
 269   dsb
 270   ldmfd SP!, {r4-r12, lr}
 271   bx    LR
 272
 273 ASM_PFX(ArmV7PerformPoUDataCacheOperation):
 274   stmfd SP!,{r4-r12, LR}
 275   mov   R1, R0                @ Save Function call in R1
 276   mrc   p15, 1, R6, c0, c0, 1 @ Read CLIDR
 277   ands  R3, R6, #0x38000000    @ Mask out all but Level of Unification (LoU)
 278   mov   R3, R3, LSR #26       @ Cache level value (naturally aligned)
 279   beq   Finished2
 280   mov   R10, #0
 281
 282 Loop4:
 283   add   R2, R10, R10, LSR #1    @ Work out 3xcachelevel
 284   mov   R12, R6, LSR R2         @ bottom 3 bits are the Cache type for this level
 285   and   R12, R12, #7            @ get those 3 bits alone
 286   cmp   R12, #2
 287   blt   Skip2                   @ no cache or only instruction cache at this level
 288   mcr   p15, 2, R10, c0, c0, 0  @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
 289   isb                           @ isb to sync the change to the CacheSizeID reg
 290   mrc   p15, 1, R12, c0, c0, 0  @ reads current Cache Size ID register (CCSIDR)
 291   and   R2, R12, #0x7            @ extract the line length field
 292   add   R2, R2, #4              @ add 4 for the line length offset (log2 16 bytes)
 293   ldr   R4, =0x3FF
 294   ands  R4, R4, R12, LSR #3     @ R4 is the max number on the way size (right aligned)
 295   clz   R5, R4                  @ R5 is the bit position of the way size increment
 296   ldr   R7, =0x00007FFF
 297   ands  R7, R7, R12, LSR #13    @ R7 is the max number of the index size (right aligned)
 298
 299 Loop5:
 300   mov   R9, R4                  @ R9 working copy of the max way size (right aligned)
 301
 302 Loop6:
 303   orr   R0, R10, R9, LSL R5     @ factor in the way number and cache number into R11
 304   orr   R0, R0, R7, LSL R2      @ factor in the index number
 305
 306   blx   R1
 307
 308   subs  R9, R9, #1              @ decrement the way number
 309   bge   Loop6
 310   subs  R7, R7, #1              @ decrement the index
 311   bge   Loop5
 312 Skip2:
 313   add   R10, R10, #2            @ increment the cache number
 314   cmp   R3, R10
 315   bgt   Loop4
 316
 317 Finished2:
 318   dsb
 319   ldmfd SP!, {r4-r12, lr}
 320   bx    LR
 321
 322 ASM_PFX(ArmDataMemoryBarrier):
 323   dmb
 324   bx      LR
 325
 326 ASM_PFX(ArmDataSyncronizationBarrier):
 327 ASM_PFX(ArmDrainWriteBuffer):
 328   dsb
 329   bx      LR
 330
 331 ASM_PFX(ArmInstructionSynchronizationBarrier):
 332   isb
 333   bx      LR
 334
 335 ASM_PFX(ArmReadVBar):
 336   # Set the Address of the Vector Table in the VBAR register
 337   mrc     p15, 0, r0, c12, c0, 0
 338   bx      lr
 339
 340 ASM_PFX(ArmWriteVBar):
 341   # Set the Address of the Vector Table in the VBAR register
 342   mcr     p15, 0, r0, c12, c0, 0
 343   # Ensure the SCTLR.V bit is clear
 344   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 345   bic     r0, r0, #0x00002000   @ clear V bit
 346   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 347   isb
 348   bx      lr
 349
 350 ASM_PFX(ArmEnableVFP):
 351   # Read CPACR (Coprocessor Access Control Register)
 352   mrc     p15, 0, r0, c1, c0, 2
 353   # Enable VPF access (Full Access to CP10, CP11) (V* instructions)
 354   orr     r0, r0, #0x00f00000
 355   # Write back CPACR (Coprocessor Access Control Register)
 356   mcr     p15, 0, r0, c1, c0, 2
 357   isb
 358   # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
 359   mov     r0, #0x40000000
 360   mcr     p10,#0x7,r0,c8,c0,#0
 361   bx      lr
 362
 363 ASM_PFX(ArmCallWFI):
 364   wfi
 365   bx      lr
 366
 367 #Note: Return 0 in Uniprocessor implementation
 368 ASM_PFX(ArmReadCbar):
 369   mrc     p15, 4, r0, c15, c0, 0  @ Read Configuration Base Address Register
 370   bx      lr
 371
 372 ASM_PFX(ArmInvalidateInstructionAndDataTlb):
 373   mcr     p15, 0, r0, c8, c7, 0      @ Invalidate Inst TLB and Data TLB
 374   dsb
 375   bx lr
 376
 377 ASM_PFX(ArmReadMpidr):
 378   mrc     p15, 0, r0, c0, c0, 5       @ read MPIDR
 379   bx      lr
 380
 381 ASM_PFX(ArmReadMidr):
 382   mrc     p15, 0, r0, c0, c0, 0       @ Read Main ID Register
 383   bx      lr
 384
 385 ASM_PFX(ArmReadTpidrurw):
 386   mrc     p15, 0, r0, c13, c0, 2    @ read TPIDRURW
 387   bx      lr
 388
 389 ASM_PFX(ArmWriteTpidrurw):
 390   mcr     p15, 0, r0, c13, c0, 2    @ write TPIDRURW
 391   bx      lr
 392
 393 ASM_PFX(ArmIsArchTimerImplemented):
 394   mrc    p15, 0, r0, c0, c1, 1     @ Read ID_PFR1
 395   and    r0, r0, #0x000F0000
 396   bx     lr
 397
 398 ASM_PFX(ArmReadIdPfr1):
 399   mrc    p15, 0, r0, c0, c1, 1     @ Read ID_PFR1 Register
 400   bx     lr
 401
 402 ASM_FUNCTION_REMOVE_IF_UNREFERENCED