1 //------------------------------------------------------------------------------
3 // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
4 // Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
6 // This program and the accompanying materials
7 // are licensed and made available under the terms and conditions of the BSD License
8 // which accompanies this distribution. The full text of the license may be found at
9 // http://opensource.org/licenses/bsd-license.php
11 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 //------------------------------------------------------------------------------
17 INCLUDE AsmMacroExport.inc
20 DC_ON EQU ( 0x1:SHL:2 )
21 IC_ON EQU ( 0x1:SHL:12 )
22 CTRL_M_BIT EQU (1 << 0)
23 CTRL_C_BIT EQU (1 << 2)
24 CTRL_B_BIT EQU (1 << 7)
25 CTRL_I_BIT EQU (1 << 12)
28 RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryByMVA
29 mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
32 RVCT_ASM_EXPORT ArmCleanDataCacheEntryByMVA
33 mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
37 RVCT_ASM_EXPORT ArmInvalidateInstructionCacheEntryToPoUByMVA
38 mcr p15, 0, r0, c7, c5, 1 ; invalidate single instruction cache line to PoU
39 mcr p15, 0, r0, c7, c5, 7 ; invalidate branch predictor
43 RVCT_ASM_EXPORT ArmCleanDataCacheEntryToPoUByMVA
44 mcr p15, 0, r0, c7, c11, 1 ; clean single data cache line to PoU
48 RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryByMVA
49 mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
53 RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryBySetWay
54 mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
58 RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
59 mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
63 RVCT_ASM_EXPORT ArmCleanDataCacheEntryBySetWay
64 mcr p15, 0, r0, c7, c10, 2 ; Clean this line
68 RVCT_ASM_EXPORT ArmInvalidateInstructionCache
69 mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
73 RVCT_ASM_EXPORT ArmEnableMmu
74 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
75 orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU
76 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
81 RVCT_ASM_EXPORT ArmDisableMmu
82 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
83 bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU
84 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
86 mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB
87 mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array
92 RVCT_ASM_EXPORT ArmDisableCachesAndMmu
93 mrc p15, 0, r0, c1, c0, 0 ; Get control register
94 bic r0, r0, #CTRL_M_BIT ; Disable MMU
95 bic r0, r0, #CTRL_C_BIT ; Disable D Cache
96 bic r0, r0, #CTRL_I_BIT ; Disable I Cache
97 mcr p15, 0, r0, c1, c0, 0 ; Write control register
102 RVCT_ASM_EXPORT ArmMmuEnabled
103 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
107 RVCT_ASM_EXPORT ArmEnableDataCache
108 ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
109 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
110 orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled
111 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
116 RVCT_ASM_EXPORT ArmDisableDataCache
117 ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
118 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
119 bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled
120 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
125 RVCT_ASM_EXPORT ArmEnableInstructionCache
126 ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
127 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
128 orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled
129 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
134 RVCT_ASM_EXPORT ArmDisableInstructionCache
135 ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
136 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
137 BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled
138 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
142 RVCT_ASM_EXPORT ArmEnableSWPInstruction
143 mrc p15, 0, r0, c1, c0, 0
144 orr r0, r0, #0x00000400
145 mcr p15, 0, r0, c1, c0, 0
149 RVCT_ASM_EXPORT ArmEnableBranchPrediction
150 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
151 orr r0, r0, #0x00000800 ;
152 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
157 RVCT_ASM_EXPORT ArmDisableBranchPrediction
158 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
159 bic r0, r0, #0x00000800 ;
160 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
165 RVCT_ASM_EXPORT ArmSetLowVectors
166 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
167 bic r0, r0, #0x00002000 ; clear V bit
168 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
172 RVCT_ASM_EXPORT ArmSetHighVectors
173 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
174 orr r0, r0, #0x00002000 ; Set V bit
175 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
179 RVCT_ASM_EXPORT ArmV7AllDataCachesOperation
180 stmfd SP!,{r4-r12, LR}
181 mov R1, R0 ; Save Function call in R1
182 mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR
183 ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)
184 mov R3, R3, LSR #23 ; Cache level value (naturally aligned)
189 add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
190 mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
191 and R12, R12, #7 ; get those 3 bits alone
193 blt Skip ; no cache or only instruction cache at this level
194 mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
195 isb ; isb to sync the change to the CacheSizeID reg
196 mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
197 and R2, R12, #&7 ; extract the line length field
198 add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
200 ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
201 clz R5, R4 ; R5 is the bit position of the way size increment
203 ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
206 mov R9, R4 ; R9 working copy of the max way size (right aligned)
209 orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11
210 orr R0, R0, R7, LSL R2 ; factor in the index number
214 subs R9, R9, #1 ; decrement the way number
216 subs R7, R7, #1 ; decrement the index
219 add R10, R10, #2 ; increment the cache number
225 ldmfd SP!, {r4-r12, lr}
228 RVCT_ASM_EXPORT ArmDataMemoryBarrier
232 RVCT_ASM_EXPORT ArmDataSynchronizationBarrier
236 RVCT_ASM_EXPORT ArmInstructionSynchronizationBarrier
240 RVCT_ASM_EXPORT ArmReadVBar
241 // Set the Address of the Vector Table in the VBAR register
242 mrc p15, 0, r0, c12, c0, 0
245 RVCT_ASM_EXPORT ArmWriteVBar
246 // Set the Address of the Vector Table in the VBAR register
247 mcr p15, 0, r0, c12, c0, 0
248 // Ensure the SCTLR.V bit is clear
249 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
250 bic r0, r0, #0x00002000 ; clear V bit
251 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
255 RVCT_ASM_EXPORT ArmEnableVFP
256 // Read CPACR (Coprocessor Access Control Register)
257 mrc p15, 0, r0, c1, c0, 2
258 // Enable VPF access (Full Access to CP10, CP11) (V* instructions)
259 orr r0, r0, #0x00f00000
260 // Write back CPACR (Coprocessor Access Control Register)
261 mcr p15, 0, r0, c1, c0, 2
263 // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
265 mcr p10,#0x7,r0,c8,c0,#0
268 RVCT_ASM_EXPORT ArmCallWFI
272 //Note: Return 0 in Uniprocessor implementation
273 RVCT_ASM_EXPORT ArmReadCbar
274 mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register
277 RVCT_ASM_EXPORT ArmReadMpidr
278 mrc p15, 0, r0, c0, c0, 5 ; read MPIDR
281 RVCT_ASM_EXPORT ArmReadTpidrurw
282 mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW
285 RVCT_ASM_EXPORT ArmWriteTpidrurw
286 mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW
289 RVCT_ASM_EXPORT ArmIsArchTimerImplemented
290 mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1
291 and r0, r0, #0x000F0000
294 RVCT_ASM_EXPORT ArmReadIdPfr1
295 mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register
298 RVCT_ASM_EXPORT ArmReadIdMmfr0
299 mrc p15, 0, r0, c0, c1, 4 ; Read ID_MMFR0 Register