ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
   4 // Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
   5 //
   6 // This program and the accompanying materials
   7 // are licensed and made available under the terms and conditions of the BSD License
   8 // which accompanies this distribution.  The full text of the license may be found at
   9 // http://opensource.org/licenses/bsd-license.php
  10 //
  11 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 //
  14 //------------------------------------------------------------------------------
  15
  16
  17     INCLUDE AsmMacroExport.inc
  18     PRESERVE8
  19
  20 DC_ON           EQU     ( 0x1:SHL:2 )
  21 IC_ON           EQU     ( 0x1:SHL:12 )
  22 CTRL_M_BIT      EQU     (1 << 0)
  23 CTRL_C_BIT      EQU     (1 << 2)
  24 CTRL_B_BIT      EQU     (1 << 7)
  25 CTRL_I_BIT      EQU     (1 << 12)
  26
  27
  28  RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryByMVA
  29   mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line
  30   bx      lr
  31
  32  RVCT_ASM_EXPORT ArmCleanDataCacheEntryByMVA
  33   mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line
  34   bx      lr
  35
  36
  37  RVCT_ASM_EXPORT ArmInvalidateInstructionCacheEntryToPoUByMVA
  38   mcr     p15, 0, r0, c7, c5, 1   ; invalidate single instruction cache line to PoU
  39   mcr     p15, 0, r0, c7, c5, 7   ; invalidate branch predictor
  40   bx      lr
  41
  42
  43  RVCT_ASM_EXPORT ArmCleanDataCacheEntryToPoUByMVA
  44   mcr     p15, 0, r0, c7, c11, 1  ; clean single data cache line to PoU
  45   bx      lr
  46
  47
  48  RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryByMVA
  49   mcr     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line
  50   bx      lr
  51
  52
  53  RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryBySetWay
  54   mcr     p15, 0, r0, c7, c6, 2        ; Invalidate this line
  55   bx      lr
  56
  57
  58  RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
  59   mcr     p15, 0, r0, c7, c14, 2       ; Clean and Invalidate this line
  60   bx      lr
  61
  62
  63  RVCT_ASM_EXPORT ArmCleanDataCacheEntryBySetWay
  64   mcr     p15, 0, r0, c7, c10, 2       ; Clean this line
  65   bx      lr
  66
  67
  68  RVCT_ASM_EXPORT ArmInvalidateInstructionCache
  69   mcr     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache
  70   isb
  71   bx      LR
  72
  73  RVCT_ASM_EXPORT ArmEnableMmu
  74   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
  75   orr     R0,R0,#1              ; Set SCTLR.M bit : Enable MMU
  76   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
  77   dsb
  78   isb
  79   bx      LR
  80
  81  RVCT_ASM_EXPORT ArmDisableMmu
  82   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
  83   bic     R0,R0,#1              ; Clear SCTLR.M bit : Disable MMU
  84   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
  85
  86   mcr     p15,0,R0,c8,c7,0      ; TLBIALL : Invalidate unified TLB
  87   mcr     p15,0,R0,c7,c5,6      ; BPIALL  : Invalidate entire branch predictor array
  88   dsb
  89   isb
  90   bx      LR
  91
  92  RVCT_ASM_EXPORT ArmDisableCachesAndMmu
  93   mrc   p15, 0, r0, c1, c0, 0           ; Get control register
  94   bic   r0, r0, #CTRL_M_BIT             ; Disable MMU
  95   bic   r0, r0, #CTRL_C_BIT             ; Disable D Cache
  96   bic   r0, r0, #CTRL_I_BIT             ; Disable I Cache
  97   mcr   p15, 0, r0, c1, c0, 0           ; Write control register
  98   dsb
  99   isb
 100   bx      LR
 101
 102  RVCT_ASM_EXPORT ArmMmuEnabled
 103   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 104   and     R0,R0,#1
 105   bx      LR
 106
 107  RVCT_ASM_EXPORT ArmEnableDataCache
 108   ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit
 109   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 110   orr     R0,R0,R1              ; Set SCTLR.C bit : Data and unified caches enabled
 111   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 112   dsb
 113   isb
 114   bx      LR
 115
 116  RVCT_ASM_EXPORT ArmDisableDataCache
 117   ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit
 118   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 119   bic     R0,R0,R1              ; Clear SCTLR.C bit : Data and unified caches disabled
 120   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 121   dsb
 122   isb
 123   bx      LR
 124
 125  RVCT_ASM_EXPORT ArmEnableInstructionCache
 126   ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit
 127   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 128   orr     R0,R0,R1              ; Set SCTLR.I bit : Instruction caches enabled
 129   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 130   dsb
 131   isb
 132   bx      LR
 133
 134  RVCT_ASM_EXPORT ArmDisableInstructionCache
 135   ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit
 136   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 137   BIC     R0,R0,R1              ; Clear SCTLR.I bit : Instruction caches disabled
 138   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 139   isb
 140   bx      LR
 141
 142  RVCT_ASM_EXPORT ArmEnableSWPInstruction
 143   mrc     p15, 0, r0, c1, c0, 0
 144   orr     r0, r0, #0x00000400
 145   mcr     p15, 0, r0, c1, c0, 0
 146   isb
 147   bx      LR
 148
 149  RVCT_ASM_EXPORT ArmEnableBranchPrediction
 150   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 151   orr     r0, r0, #0x00000800   ;
 152   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 153   dsb
 154   isb
 155   bx      LR
 156
 157  RVCT_ASM_EXPORT ArmDisableBranchPrediction
 158   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 159   bic     r0, r0, #0x00000800   ;
 160   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 161   dsb
 162   isb
 163   bx      LR
 164
 165  RVCT_ASM_EXPORT ArmSetLowVectors
 166   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 167   bic     r0, r0, #0x00002000   ; clear V bit
 168   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 169   isb
 170   bx      LR
 171
 172  RVCT_ASM_EXPORT ArmSetHighVectors
 173   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 174   orr     r0, r0, #0x00002000   ; Set V bit
 175   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 176   isb
 177   bx      LR
 178
 179  RVCT_ASM_EXPORT ArmV7AllDataCachesOperation
 180   stmfd SP!,{r4-r12, LR}
 181   mov   R1, R0                ; Save Function call in R1
 182   mrc   p15, 1, R6, c0, c0, 1 ; Read CLIDR
 183   ands  R3, R6, #&7000000     ; Mask out all but Level of Coherency (LoC)
 184   mov   R3, R3, LSR #23       ; Cache level value (naturally aligned)
 185   beq   Finished
 186   mov   R10, #0
 187
 188 Loop1
 189   add   R2, R10, R10, LSR #1    ; Work out 3xcachelevel
 190   mov   R12, R6, LSR R2         ; bottom 3 bits are the Cache type for this level
 191   and   R12, R12, #7            ; get those 3 bits alone
 192   cmp   R12, #2
 193   blt   Skip                    ; no cache or only instruction cache at this level
 194   mcr   p15, 2, R10, c0, c0, 0  ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
 195   isb                           ; isb to sync the change to the CacheSizeID reg
 196   mrc   p15, 1, R12, c0, c0, 0  ; reads current Cache Size ID register (CCSIDR)
 197   and   R2, R12, #&7            ; extract the line length field
 198   add   R2, R2, #4              ; add 4 for the line length offset (log2 16 bytes)
 199   ldr   R4, =0x3FF
 200   ands  R4, R4, R12, LSR #3     ; R4 is the max number on the way size (right aligned)
 201   clz   R5, R4                  ; R5 is the bit position of the way size increment
 202   ldr   R7, =0x00007FFF
 203   ands  R7, R7, R12, LSR #13    ; R7 is the max number of the index size (right aligned)
 204
 205 Loop2
 206   mov   R9, R4                  ; R9 working copy of the max way size (right aligned)
 207
 208 Loop3
 209   orr   R0, R10, R9, LSL R5     ; factor in the way number and cache number into R11
 210   orr   R0, R0, R7, LSL R2      ; factor in the index number
 211
 212   blx   R1
 213
 214   subs  R9, R9, #1              ; decrement the way number
 215   bge   Loop3
 216   subs  R7, R7, #1              ; decrement the index
 217   bge   Loop2
 218 Skip
 219   add   R10, R10, #2            ; increment the cache number
 220   cmp   R3, R10
 221   bgt   Loop1
 222
 223 Finished
 224   dsb
 225   ldmfd SP!, {r4-r12, lr}
 226   bx    LR
 227
 228  RVCT_ASM_EXPORT ArmDataMemoryBarrier
 229   dmb
 230   bx      LR
 231
 232  RVCT_ASM_EXPORT ArmDataSynchronizationBarrier
 233   dsb
 234   bx      LR
 235
 236  RVCT_ASM_EXPORT ArmInstructionSynchronizationBarrier
 237   isb
 238   bx      LR
 239
 240  RVCT_ASM_EXPORT ArmReadVBar
 241   // Set the Address of the Vector Table in the VBAR register
 242   mrc     p15, 0, r0, c12, c0, 0
 243   bx      lr
 244
 245  RVCT_ASM_EXPORT ArmWriteVBar
 246   // Set the Address of the Vector Table in the VBAR register
 247   mcr     p15, 0, r0, c12, c0, 0
 248   // Ensure the SCTLR.V bit is clear
 249   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 250   bic     r0, r0, #0x00002000   ; clear V bit
 251   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 252   isb
 253   bx      lr
 254
 255  RVCT_ASM_EXPORT ArmEnableVFP
 256   // Read CPACR (Coprocessor Access Control Register)
 257   mrc     p15, 0, r0, c1, c0, 2
 258   // Enable VPF access (Full Access to CP10, CP11) (V* instructions)
 259   orr     r0, r0, #0x00f00000
 260   // Write back CPACR (Coprocessor Access Control Register)
 261   mcr     p15, 0, r0, c1, c0, 2
 262   isb
 263   // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
 264   mov     r0, #0x40000000
 265   mcr     p10,#0x7,r0,c8,c0,#0
 266   bx      lr
 267
 268  RVCT_ASM_EXPORT ArmCallWFI
 269   wfi
 270   bx      lr
 271
 272 //Note: Return 0 in Uniprocessor implementation
 273  RVCT_ASM_EXPORT ArmReadCbar
 274   mrc     p15, 4, r0, c15, c0, 0  //Read Configuration Base Address Register
 275   bx      lr
 276
 277  RVCT_ASM_EXPORT ArmReadMpidr
 278   mrc     p15, 0, r0, c0, c0, 5     ; read MPIDR
 279   bx      lr
 280
 281  RVCT_ASM_EXPORT ArmReadTpidrurw
 282   mrc     p15, 0, r0, c13, c0, 2    ; read TPIDRURW
 283   bx      lr
 284
 285  RVCT_ASM_EXPORT ArmWriteTpidrurw
 286   mcr     p15, 0, r0, c13, c0, 2   ; write TPIDRURW
 287   bx      lr
 288
 289  RVCT_ASM_EXPORT ArmIsArchTimerImplemented
 290   mrc    p15, 0, r0, c0, c1, 1     ; Read ID_PFR1
 291   and    r0, r0, #0x000F0000
 292   bx     lr
 293
 294  RVCT_ASM_EXPORT ArmReadIdPfr1
 295   mrc    p15, 0, r0, c0, c1, 1     ; Read ID_PFR1 Register
 296   bx     lr
 297
 298  END